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| digital controller for isolated power supply applications data sheet adp1046a rev. 0 document feedbac k information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical suppor t www.analog.com features integrates all typical pwm controller functions 7 pwm control signals digital control loop integrated programmable loop filters programmable voltage line feedforward dedicated soft start filter remote and local voltage sense primary and secondary side current sense synchronous rectifier control current sharing orfet control i 2 c interface extensive fault detection and protection extensive programming and telemetry fast digital calibration user accessible eeprom applications ac-to-dc power supplies isolated dc-to-dc power supplies redundant power supply systems server, storage, network, and communications infrastructure general description the adp1046a is a flexible, digital secondary side controller designed for ac-to-dc and isolated dc-to-dc secondary side applications. the adp1046a is pin-compatible with the adp1043a and offers several enhancements and new features, including voltage feedforward and improved loop response to maximize efficiency. the adp1046a is optimized for minimal component count, maximum flexibility, and minimum design time. features include local and remote voltage sense, primary and secondary side current sense, digital pulse-width modulation (pwm) generation, current sharing, and redundant orfet control. the control loop digital filter and compensation terms are integrated and can be programmed over the i 2 c interface. programmable protection features include overcurrent protection (ocp), over- voltage protection (ovp), undervoltage lockout (uvlo), and overtemperature protection (otp). the built-in eeprom provides extensive programming of the integrated loop filter, pwm signal timing, inrush current, and soft start timing and sequencing. reliability is improved through a built-in checksum and programmable protection circuits. a comprehensive gui is provided for easy design of loop filter characteristics and programming of the safety features. the industry-standard i 2 c bus provides access to the many monitoring and system test functions. the adp1046a is available in a 32-lead lfcsp and operates from a single 3.3 v supply. typical application circuit res rtd add vcore flagin pson pgood2 pgood1 sda scl vdd dgnd agnd outa outb outc outd outaux cs1 sr1 sr2 acsns vs1 gate vs3+ vs3? shareo sharei driver i coupler ? driver vs2 driver dc inpu t load microcontroller cs2? cs2+ pgnd v dd adp1046a 11012-001 figure 1.
adp1046a data sheet rev. 0 | page 2 of 88 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical application circuit ............................................................. 1 revision hist ory ............................................................................... 3 specifications ..................................................................................... 4 absolute maximum ratings ............................................................ 9 thermal resist ance ...................................................................... 9 soldering ........................................................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 theory of operation ...................................................................... 14 current sense .............................................................................. 15 voltage sense and control loop .............................................. 16 adcs ............................................................................................ 16 vs1 operation (vs1) ................................................................. 16 vs2 operation (vs2) ................................................................. 17 vs3 operation (vs3+, vs3?) ................................................... 17 voltage line feedforward and acsns .................................... 17 digital filter ................................................................................ 17 pwm and synchronous rectifier outputs (outa, outb, outc, outd, outaux, sr1, sr2) ........ 18 synchronous rectification ........................................................ 19 synchronous rectifier (sr) delay ............................................ 19 light load mode ........................................................................ 19 modulation limit ....................................................................... 19 soft start ...................................................................................... 20 orfet control (gate pin) ..................................................... 22 vdd ............................................................................................. 24 vdd/vcore ovlo ................................................................ 24 power good ................................................................................. 24 current sharing .......................................................................... 25 power sup ply system and fault monitoring ............................... 27 flags .............................................................................................. 27 monitoring functions ................................................................ 27 voltage readings ........................................................................ 27 current readings ........................................................................ 27 power readings ........................................................................... 28 po wer monitoring accuracy ..................................................... 28 first flag fault id and value registers ................................... 28 external flag input (flagin pin) .......................................... 28 temperature readings (rtd pin) ........................................... 28 overtemperature protection (otp) ........................................ 29 overcurrent prot ection (ocp) ................................................ 29 constant current mode ............................................................ 30 overvoltage protection (ovp) ................................................. 30 undervoltage protection (uvp) .............................................. 31 ac sense (acsns) ..................................................................... 31 volt - second balance .................................................................. 31 digital load line and slew rate .............................................. 32 power supply calibration and trim ............................................ 33 cs1 trim ...................................................................................... 33 cs2 trim ...................................................................................... 33 voltage calibration and trim ................................................... 34 output voltage setting (vs3+, vs3? trim) ........................... 34 vs1 trim ...................................................................................... 34 vs2 trim ...................................................................................... 34 rtd/otp trim .......................................................................... 34 acsns calibration and trim ................................................... 35 layout guidelines ........................................................................... 36 cs2+ and cs2? ........................................................................... 36 vs3+ and vs3? ........................................................................... 36 vdd ............................................................................................. 36 sda and scl .............................................................................. 36 cs1 ............................................................................................... 36 exposed pad ................................................................................ 36 vcore ........................................................................................ 36 res ............................................................................................... 36 rtd .............................................................................................. 36 agnd, dgnd, and pgnd ...................................................... 36 i 2 c interface communication ...................................................... 37 i 2 c overview ............................................................................... 37 i 2 c address .................................................................................. 37 data transfer ............................................................................... 37 general call support ................................................................. 39 10- bit addressing ....................................................................... 39 fast mo de .................................................................................... 39 repeated start condition .......................................................... 39 electrical specifications ............................................................. 39 data sheet adp1046a rev. 0 | page 3 of 88 fault conditions .......................................................................... 39 ? timeout condition ..................................................................... 39 ? data transmission faults ........................................................... 39 ? data content faults .................................................................... 39 ? eeprom .......................................................................................... 41 ? eeprom overview .................................................................... 41 ? page erase operation ................................................................. 41 ? read operation (byte read and block read) ......................... 41 ? write operation (byte write and block write) ...................... 42 ? eeprom password..................................................................... 42 ? downloading eeprom settings to internal registers .......... 42 ? saving register settings to the eeprom ................................ 43 ? eeprom crc checksum ......................................................... 43 ? software gui ................................................................................... 44 ? register listing ................................................................................ 45 ? detailed register descriptions ...................................................... 48 ? fault registers .............................................................................. 48 ? value registers ............................................................................. 51 ? current sense and current limit registers ............................ 54 ? voltage sense registers .............................................................. 59 id registers .................................................................................. 62 ? pwm and synchronous rectifier timing registers .............. 63 ? digital filter programming registers ...................................... 73 ? soft start filter programming registers .................................. 75 ? extended functions registers ................................................... 75 ? eeprom registers ..................................................................... 79 ? resonant mode operation ............................................................. 82 ? resonant mode enable ............................................................... 82 ? pwm timing in resonant mode ............................................. 82 ? synchronous rectification in resonant mode ........................ 82 ? adjusting the timing of the pwm outputs ........................... 83 ? frequency limit setting ............................................................. 83 ? feedback control in resonant mode ....................................... 83 ? soft start in resonant mode ...................................................... 83 ? light load operation (burst mode) ........................................ 83 ? outaux pin in resonant mode ............................................. 83 ? protections in resonant mode .................................................. 83 ? resonant mode register descriptions ..................................... 84 ? outline dimensions ........................................................................ 88 ? ordering guide ........................................................................... 88 ? revision history 2/13revision 0: initial version adp1046a data sheet rev. 0 | page 4 of 88 specifications v dd = 3.0 v to 3.6 v, t a = ?40c to +125c, unless otherwise noted. fsr = full - scale range. table 1 . parameter symbol test conditions/comments min typ max unit supply supply voltage v dd 4.7 f capacitor connected to agnd 3.0 3.3 3.6 v supply current i dd normal operation (pson is high or low) 20 ma during eeprom programming (40 ms) i dd + 8 ma shutdown ( v dd below uvlo) 100 a power - on reset power - on reset v dd rising 3.0 v uvlo v dd falling 2.75 2.85 2.97 v uvlo hysteresis 40 mv ovlo 3.8 4.0 4.1 v ovlo debounce when set to 2 s 2.0 s when set to 500 s 500 s vcore pin 0.33 f capacitor connected to d gnd output voltage t a = 25c 2.4 2.5 2.7 v oscillator and pll pll frequency res = 10 k? (0.1%) 190 200 210 mhz outa, outb, outc, outd, outaux, sr1, sr2, gate pins output low voltage v ol source current = 10 ma 0.4 v output high voltage v oh source current = 10 ma v dd ? 0.4 v rise time c load = 50 pf 3.5 ns fall time c lo ad = 50 pf 1.5 ns vs1, vs2, vs3 low speed adc s input voltage range v in differential voltage from vs1, vs2 to pgnd, and from vs3+ to vs3? 0 1 1.6 v usable input voltage range 0 1.4 v adc clock frequency 1.56 mhz register update rate 1 0 ms voltage sense measurement accuracy factory trimmed at 1.0 v 0% to 100 % of usable input voltage range ?3.0 +3.0 % fsr ?48 +48 mv 10% to 90% of usable input voltage range ?2.0 +2.0 % fsr ?32 +32 mv 900 mv to 1.1 v ?1.0 +1.0 % fsr ?16 +16 mv temperature coefficient 65 ppm/ c leakage current 1.0 a voltage sense measurement resolution 12 bits common - mode voltage offset ?0.25 +0.25 % fsr voltage differential from vs3? to pgnd ?200 +200 mv vs1 accura te ovp speed register 0x32[1:0] = 00; e quivalent resolution is 7 bit s 80 s vs1 ovp threshold accuracy relative to nominal voltage (1 v) on vs1 ?2.0 +2.0 % fsr vs2 and vs3 ovp speed register 0x33[ 1 : 0 ] = 00; e quivalent resolution is 7 bit s 80 s vs2 and vs3 ovp threshold accuracy relative to nominal voltage (1 v) on vs2 and vs3 ?2.0 +2.0 % fsr data sheet adp1046a rev. 0 | page 5 of 88 parameter symbol test conditions/comments min typ max unit vs3 high speed adc equivalent sampling frequency f samp f sw khz equivalent resolution f sw = 390.6 khz 6 bits dynamic range 30 mv vs1 fast ovp comparator threshold accuracy at f actory trim of 1.2 v 1 1. 60 % at other thresholds (0.8 v to 1.6 v) ?2.0 6 + 2.0 6 % propagation delay does not include debounce time (register 0x 0a[7] = 1) 40 ns vs1 uvp digital comparator v s1 uvp accuracy ?2.0 +2.0 % fsr propagation delay does not include debounce time ( register 0x0b[ 3 ] = 1 ) 80 s ac sense comparator pwm and resonant mode input voltage threshold 0.4 0.45 0.5 v propagation delay from acsns threshold to sr x rising edge (resonant mode only) 160 ns adc clock frequency 1.56 mhz input voltage range v acsns 0 1 1.6 v usable input voltage range 0 1.4 v sampling frequency for i 2 c reporting 100 hz sampling period for feedforward equivalent resolut ion is 11 bits 10 s measurement accuracy factory trimmed at 1.0 v 0% to 100% of usable input voltage range ?5.0 +3.0 % fsr 10% to 90% of usable input voltage range ?2.0 +2.0 % fsr 900 mv to 1.1 v ?1.0 + 1.0 % fsr ?16 +16 mv leakage current 1.0 a current sense 1 (cs1 pin) input voltage range v in 0 1 1.4 v usable input voltage range 0 1.3 v adc clock frequency 1.56 mhz register update r ate 10 ms current sense measurement accuracy factory trimmed at 0.7 v ; tested under dc input conditions 10% to 50% of usable input voltage range ?3.0 +3.0 % fsr ?41.4 +41.4 mv 0% to 100 % of usable input voltage range ?6.0 +3.0 % fsr ?84 +42 mv 40% to 60 % of usable input voltage range ?1.0 +1.0 % fsr current sense measurement resolution 12 bits cs1 fast ocp threshold 1.18 4 1.2 1.21 6 v cs1 fast ocp speed 80 100 ns cs1 accurate ocp dc accuracy 10% to 90 % of usable input voltage range ?2.0 +2.0 % fsr ?28 +28 mv cs1 accurate ocp speed 2.62 5.24 ms leakage current 1.0 a adp1046a data sheet rev. 0 | page 6 of 88 parameter symbol test conditions/comments min typ max unit current sense 2 (cs2+, cs2? pins) input voltage range v in differe ntial voltage from cs2+ to cs2? , lsb = 29.297 v 0 120 mv usable input voltage range 0 110 mv adc clock frequency 1.56 mhz temperature coefficient 120 mv range 0 mv to 100 mv 78 ppm/ c 0 mv to 50 mv 70 ppm/ c 60 mv range 0 mv to 50 mv 156 ppm/ c 0 mv to 25 mv 140 ppm/ c current sense measurement 120 mv s etting 0 mv to 110 mv ?2.1 +2.1 % fsr ?2.52 +2.52 mv 60 mv setting 0 mv to 55 mv ?4.2 +4.2 % fsr ?5.04 +5.04 mv current sense measurement accuracy w ith 0.01% l evel s hifting r esistors 120 mv s etting 0 mv to 100 mv, v dd = 3.3 v ?0.9 +0.9 % fsr ?1.08 +1.08 mv 60 mv setting 0 mv to 55 mv , v dd = 3.3 v ?1.8 +1.8 % fsr ?2.16 +2.16 mv current sense measurement resolution 12 bits cs2 accurate ocp speed 2.62 5.24 ms current sink (high side) 2 ma current source (low side) 200 a common - mode voltage at the cs2+ and cs2? pins to achieve cs2 measurement accuracy 0.8 1.0 1.4 v orfet protection (cs2+, cs2?) low - side and high - side cu rrent sensing fast orfet accuracy ?3 mv setting +3.5 ?3.00 ?9.5 mv ?6 mv setting +0.29 ?6.21 ?12.71 mv ?9 mv setting ?2.68 ?9.43 ?16.18 mv ?12 mv setting ?5.89 ?12.64 ?19.39 mv ?15 mv setting ?9.01 ?15.86 ?22.71 mv ?18 mv setti ng ?12.22 ?19.07 ?25.92 mv ?21 mv setting ?15.29 ?22.29 ?29.29 mv ?24 mv setting ?18.50 ?25.50 ?32.50 mv fast orfet speed debounce = 40 ns 110 150 ns rtd temperature sense adc clock frequency 1.56 mhz input voltage range rtd to agnd 0 1.6 v usable input voltage range 0 1.3 v source current factory trimmed to 46 a ( register 0x 11 set to 0xe6) 44.35 46 47.65 a current source set to 10 a 9.25 10.1 10. 8 5 a current source set to 20 a 18.35 20.1 21.85 a current source s et to 30 a 28.45 30.2 31.95 a current source set to 40 a 38.45 40.3 41.95 a source c urrent f ine s etting see register 0x11[5:0] 160 na rtd adc register update rate 10 ms resolution 12 bits data sheet adp1046a rev. 0 | page 7 of 88 parameter symbol test conditions/comments min typ max unit measurement accuracy factory trimmed a t 1 v 1 0 mv to 160 mv ?0.5 +0.5 % fsr ?8 +8 mv 0% to 100% of usable input voltage range ?3.0 +3.0 % fsr ?42 +42 mv temperature readings using internal linearization scheme rtd source set to 46 a (register 0x11 set to 0xe6); ntc r0 = 100 k ? , 1% ; beta = 4250, 1% ; r ext = 16.5 k ? , 1% 25c to 100c 7 c 100c to 125c 5 c otp threshold accuracy t = 85c with 100 k?||16.5 k? ?0.9 +0.25 % fsr ?14.4 +4 mv t = 100c with 100 k?||16.5 k? ?0.5 +1.1 % fsr ?8 +17.6 mv comparator speed 10.5 ms otp threshold hysteresis 16 mv pgood1, pgood2, shareo pins open - drain outputs output low voltage v ol 0.4 v pson, sharei pins digital inputs input low voltage v il 0. 8 v input high voltage v ih v dd ? 0. 8 v leakage c urrent 1.0 a flagin pin digital input input low voltage v il 0. 4 v input high voltage v ih v dd ? 0. 8 v propagation delay does not include debounce time ( register 0x0 a [3] = 1 ); flag action set to disable psu 200 ns leakage current 1.0 a gate pin output low voltage v ol 0.4 v output high voltage v oh v dd ? 0.4 v sda/scl pins v dd = 3.3 v input low voltage v il 0. 8 v input high voltage v ih v dd ? 0. 8 v output low voltage v ol 0.4 v leakage current 1.0 a serial bus timing see figure 2 clock operating frequency 10 100 400 khz bus - free time t buf between stop and start condition s 1.3 s start hold time t hd ; sta hold time after (repeated) start condition ; after this per iod, the first clock is generated 0.6 s start setup time t su ; sta repeated start condition setup time 0.6 s stop setup t ime t su ; sto 0.6 s sda setup time t su;dat 100 ns sda hold time t hd ; dat for readback 125 ns for write 300 ns scl l ow timeout t timeout 25 35 ms scl low period t low 1.3 s scl high period t high 0.6 s clock low extend time t lo ; sext 25 ms scl, sda fall time t f 20 300 ns scl, sda rise t ime t r 20 300 ns adp1046a data sheet rev. 0 | page 8 of 88 parameter symbol test conditions/comments min typ max unit eeprom reliability endurance 1 t j = 85c 1 0,000 cycles t j = 125c 1 000 cycles data retention 2 t j = 85c 20 years t j = 125c 10 years 1 endur ance is qualified as per jedec standard 22, method a117, and is measured at ?40c, +25c, +85c, and +125c. endurance condit ions are subject to change pending eeprom qualification. 2 retention lifetime equivalent at junction temperature (t j ) = 85c as per jedec standard 22, method a117. the derated retention lifetime equivalent at junction temperature t j = 125 c is 2.87 years and is subject to change pending eeprom qualification. timing diagram scl sda p s t buf t hd;sta t hd;dat t high t su;dat t hd;sta t su;sta t su;sto t low t r t f s p 1 1012-103 figure 2 . serial bus timing diagram data sheet adp1046a rev. 0 | page 9 of 88 absolute maximum rat ings table 2 . paramete r rating supply voltage (continuous) , v dd 4.2 v digital pins: outa, outb, outc, outd, outaux, sr1, sr2, gate, pgood1, pgood2 ?0.3 v to v dd + 0.3 v vs3? to pgnd, agnd, dgnd ?0.3 v to +0.3 v vs1, vs2, vs3 + , acsns ?0.3 v to v dd + 0.3 v rtd, add ?0.3 v to v dd + 0.3 v cs1, cs2+, cs2? ?0.3 v to v dd + 0.3 v flagin, pson ?0.3 v to v dd + 0.3 v sda, scl ?0.3 v to v dd + 0.3 v shareo, sharei ?0.3 v to v dd + 0.3 v operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c peak solder reflow temperature snpb assemblies (10 sec to 30 sec) 240c rohs - compliant assemblies (20 sec to 40 sec) 260c esd charged device model 1.5 kv esd human body model 3.5 kv stresses above those listed under absolute max imum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to abso lute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . thermal resistance package type ja jc unit 32- lead lfcsp 44.4 6.4 c/w soldering it is important to follow the correct guidelines when laying out the pcb footprint for the adp1046a and when soldering the part onto the pcb. for detailed information about these guide - lines, see the an - 772 application note . esd caution adp1046a data sheet rev. 0 | page 10 of 88 pin configuration an d function descripti ons 1 vs2 2 agnd 3 vs1 4 cs2? 5 cs2+ 6 acsns 7 cs1 8 pgnd 24 sharei 23 shareo 22 pgood1 21 pgood2 20 flagin 19 pson 18 sda 17 scl 9 sr1 10 sr2 1 1 ou t a 12 outb 13 outc 14 outd 15 ou t aux 16 ga te 32 vs3+ 31 vs3? 30 res 29 add 28 rtd 27 vdd 26 vcore 25 dgnd adp1046 a t op view (not to scale) notes 1. the adp1046a has an exposed thermal pad on the underside of the package. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the pcb agnd plane. 1 1012-003 figure 3 . pi n configuration table 4 . pin function descriptions pin no. mnemonic description 1 vs2 power supply output voltage sense input. this signal is referenc ed to pgnd and is the input to a low frequency - adc. nominal voltage at this pin should be 1 v. the resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. 2 agnd analog ground. this pin is the ground for the analog circuitry and the return for the vdd pin of the adp1046a . 3 vs1 local output voltage sense input. this signal is referenc ed to pgnd. nominal voltage at this pin should be 1 v. the resistor divi der on this input must have a tolerance specification of 0.5% or better to allow for trimming. 4 cs2? inverting differential current sense input. nominal voltage at this pin should be 1 v for best operation. when using low - side current sensing, place a 5 k ? resistor between the sense resistor and this pin. when using high - side current sensing in a 12 v application, place a 5.5 k ? resistor between the sense resistor and this pin. when using high - side current sensing with a voltage other than 12 v , use th e following formula t o calculate the resistor value: r = ( v out ? 1)/2 ma. a 0.1% resistor must be use d to connect this circuit. i f this pin is not used , connect it to pgnd and set cs2 to high - side current sense mode (set bit 2 of register 0x27). it is recommended that a 500 pf to 1000 pf capacitor be connected either across the resistor or from this pin to agnd. 5 cs2+ noni nverting differential current sense input. nominal voltage at this pin should be 1 v for best operation. when using low - side current sensing, place a 5 k ? resistor between the sense resistor and this pin. when using high - side current sensing in a 12 v appl ication, place a 5.5 k ? resistor between the sense resistor and this pin. when using high - side current sensing with a voltage other than 12 v, use th e following formula to calculate the resistor value: r = (v out ? 1)/2 ma. a 0.1% resistor must be used to c onnect this circuit. if this pin is not used, connect it to pgnd and set cs2 to high - side current sense mode (set bit 2 of register 0x27). it is recommended that a 500 pf to 1000 pf capacitor be connected either across the resistor or from this pin to agn d. 6 acsns ac sense input. this input is connected upstream of the main output inductor through a resistor divider network. the nominal voltage for this circuit is 0.45 v. this pin is also connected to the voltage feedforward adc (nominal voltage 1 v). th is signal is referenc ed to pgnd. 7 cs1 primary side current sense input. this pin is connected to the primary side current sensing adc and to the fast ocp comparator. this signal is referenced to pgnd. the resistors on this input must have a tolerance spe cification of 0.5% or better to allow for trimming. i f this pin is not used , c onnect it to pgnd . 8 pgnd power ground. this pin is the ground connection for the main power rail of the power supply and is the reference for all voltage and current sensing ot her than cs2 and vs3. star connect to agnd. 9 sr1 synchronous rectifier output. this pwm output connects to the input of a fet driver. this signal is referenc ed to agnd. this pin can be disabled when not in use. 10 sr2 synchronous rectifier output. thi s pwm output connects to the input of a fet driver. this signal is referenc ed to agnd. this pin can be disabled when not in use. 11 outa pwm output for primary side switch. this signal is referenced to agnd. this pin c an be disabled when not in use. 12 o utb pwm output for primary side switch. this signal is referenced to agnd. this pin can be disabled when not in use. 13 outc pwm output for primary side switch. this signal is referenced to agnd. this pin can be disabled when not in use. data sheet adp1046a rev. 0 | page 11 of 88 pin no. mnemonic description 14 outd pwm outp ut for primary side switch. this signal is referenced to agnd. this pin can be disabled when not in use. 15 outaux auxiliary pwm output. this signal is referenced to agnd. this pin can be disabled when not in use. 16 gate orfet gate drive output. this si gnal is referenc ed to agnd. if this pin is not use d , leave it floating. 17 scl i 2 c serial clock input. this signal is referenced to agnd. 18 sda i 2 c serial data input and output (open drain). this signal is referenced to agnd. 19 pson power supply on in put. this signal is referenc ed to agnd. this pin is the hardware p son control signal. it is recom mended that a 1 nf capacitor be connected from the pson pin to agnd for noise debouncing and decoupling. 20 flagin flag input. an external signal can be input at this pin to generate a flag condition. 21 pgood2 power - good output (open drain). this signal is referenc ed to agnd. this pin is controlled by the pgood2 flag. this pin is set by a programmable combination of internal flags. i f this pin is not used , c o nnect it to a gnd . 22 pgood1 power - good output (open drain). this signal is referenc ed to agnd. this pin is controlled by the pgood1 flag. this pin is set by a programmable combination of internal flags. i f this pin is not used , c onnect it to a gnd . 23 sha reo share bus output voltage pin. connect this pin to 3.3 v through a pull - up resistor (typically 2.2 k?) . when configured for a digital share bus, this pin is a digital output. this signal is referenced to agnd. if this pin is not used, connect it to agn d . 24 sharei share bus feedback pin. connect this pin to the shareo pin. this signal is referenc ed to agnd. i f this pin is not used , c onnect it to a gnd . 25 dgnd digital ground. this pin is the ground reference for the digital circuitry of the adp1046a . star connect to agnd. 26 vcore output of the 2.5 v regulator. connect a decoupling capacitor of at least 330 nf (1 f maximum) from this pin to dgnd as close to the ic as possible to minim ize pcb trace length. it is recommended that the vcore pin not be used as a reference or to generate other logic levels using resistive dividers. 27 vdd positive supply input. this signal is referenc ed to agnd. connect a 4.7 f decoupling capacitor from this pin to agnd as clo se to the ic as possible to minimize pcb trace length. 28 rtd thermistor input. place a thermistor ( 100 k ? , 1% ; beta = 4250, 1% ) in parallel with a 16.5 k? , 1% resistor. this pin is referenced to agnd. i f this pin is not used , c onnect it to a gnd . 29 add address select input . this pin is used to program the i 2 c address. connect a resistor from add to agn d. this signal is referenc ed to agnd. 30 res resistor input. this pin sets up the internal voltage reference for the adp1046a . connect a 10 k ? , 0.1% resistor from res to agnd. this signal is referenc ed to agn d. 31 vs3? inverting remote voltage sense input. there should be a low ohmic connection to agnd. the resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. connect a 0.1 f capacitor from vs3? to agnd. 32 vs3+ noni nverting remote voltage sense input. this signal is referenc ed to vs3?, and the nominal input voltage at this pin is 1 v. the resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. this pin is the input to the high frequency - adc. ep exposed pad . the adp1046a has an exposed thermal pad on the underside of the package. for increased reliability of the solder joints and maximum thermal capabili ty, it is recommended that the pad be soldered to the pcb agnd plane. adp1046a data sheet rev. 0 | page 12 of 88 typical performance characteristics 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?60 ?40 ?20 0 20 40 60 80 100 120 140 vs1 adc accuracy (%fsr) temperature (c) max spec min spec min mean max 1 1012-400 figure 4 . vs1 adc accuracy vs. temperature (from 10% to 90% of fsr) 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?60 ?40 ?20 0 20 40 60 80 100 120 140 vs2 adc accuracy (%fsr) temperature (c) max spec min spec min mean max 1 1012-401 figure 5 . vs2 adc acc uracy vs. temperature (from 10% to 90% of fsr) 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?60 ?40 ?20 0 20 40 60 80 100 120 140 vs3 adc accuracy (%fsr) temperature (c) max spec min spec min mean max 1 1012-402 figure 6 . vs3 adc accuracy vs. temperature (from 10% to 90% of fsr) 4 ?4 ?3 ?2 ?1 0 1 2 3 ?60 ?40 ?20 0 20 40 60 80 100 120 140 cs1 adc accuracy (%fsr) temperature (c) max spec min spec min mean max 11012-403 figure 7 . cs1 adc accuracy vs. temperature (from 10% to 50 % of fsr) 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 1.0 0.5 1.5 2.0 ?60 ?40 ?20 0 20 40 60 80 100 120 140 cs2 adc accuracy (%fsr) temperature (c) max spec min spec min mean max 1 1012-404 figure 8 . cs2 adc accuracy vs. temperature (from 10% to 90% of fsr) 4 ?4 ?3 ?2 ?1 0 1 2 3 ?60 ?40 ?20 0 20 40 60 80 100 120 140 rtd adc accuracy (%fsr) temperature (c) max spec min spec min max mean 1 1012-408 figure 9 . rtd adc accuracy vs. temperature (from 10% to 90% of fsr) data sheet adp1046a rev. 0 | page 13 of 88 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 1.0 0.5 1.5 2.0 ?60 ?40 ?20 0 20 40 60 80 100 120 140 acsns adc accuracy (%fsr) temperature (c) max spec min spec mean max 1 1012-406 min figure 10 . acsns adc accuracy vs. temperature (f rom 10% to 90% of fsr) 1.220 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 ?60 ?40 ?20 0 20 40 60 80 100 120 140 cs1 fast ocp threshold (v) temperature (c) min max max spec min spec mean 11012-405 figure 11 . cs1 fast ocp threshold vs. temperature 1.28 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 ?60 ?40 ?20 0 20 40 60 80 100 120 140 vs1 fast ocp threshold (v) temperature (c) min max max spec min spec mean 11012-500 figure 12 . vs1 fast ocp threshold vs. temperature adp1046a data sheet rev. 0 | page 14 of 88 theory of operation the a dp1046a is a secondary side controller for switch mode power supplies. it is designed for use in isolated redundant applications. the adp1046a integrates the typical functions that are needed to control a powe r supply, such as ? output voltage sense and feedback ? voltage line feedforward control ? digital loop filter compensation ? pwm generation ? current sharing ? current, voltage, and temperature sense ? orfet control ? housekeeping and i 2 c interface ? calibration and trimmi ng the main function of controlling the output voltage is performed using the feedback adcs, the digital loop filter, and the pwm block. the feedback adcs use a multipath approach (patent pending). the adp1046a combines a high speed, low resolution (fast and coarse) adc with a low speed, high resolution (slow and accurate) adc. loop compensation is implemented using the digital filter. this proportional, integral, derivative (pid) filter is implemented in the di gital domain to allow easy programming of filter charac - teristics, which is of great value in customizing and debugging designs. the pwm block generates up to seven programmable pwm outputs for control of fet drivers and synchronous rectification fet driv ers. this programmability allows many traditional and unique switching topologies to be realized. a current share bus interface is provided for paralleling multiple power supplies. the adp1046a also has hot - swa p orfet sense and control for n + 1 redundant power supplies. conventional power supply housekeeping features, such as remote and local voltage sense and primary and secondary side current sense, are included. an extensive set of protections is offered, in cluding overvoltage protection (ovp), overcurrent protection (ocp), overtemperature protection (otp), undervoltage protec - tion (uvp), ground continuity monitoring (voltage continuity), and ac sense. all these features are programmable through the i 2 c bus i nter - face. this bus interface is also used to calibrate the power supply. other information that is useful for power monitoring, such as input current, output current, and fault flags, is also available through the i 2 c bus interface. the internal eeprom ca n store all programmed values and allows standalone control without a microcontroller. a free, downloadable gui is available and provides all the necessary software to program the adp1046a . to obtain the latest software and a user guide, visit http://www.analog.com/digitalpower . the adp1046a operates from a single 3.3 v supply and is specified from ?40c to +125c. res vs3? vs3+ pgood1 vdd gate pgnd acsns vs1 outa outb sr1 sr2 outc outd cs1 pson scl sda cs2? cs2+ vs2 vcore agnd outaux pgood2 sharei flagin dgnd rtd add adc adc adc adc adc uvlo pwm engine v ref ldo adc adc 8kb eeprom digital core i 2 c interface pwm osc 1.2v + ? 0.45v + ? v_ovp shareo adp1046a 11012-002 figure 13 . simplified block diagram data sheet adp1046a rev. 0 | page 15 of 88 current sense the adp1046a has two current sense inputs: cs1 and cs2. these inputs sense, protect, and control the primary input current, seco ndary output current, and the share bus information. they can be calibrated to reduce errors due to external components. cs1 operation (cs1) cs1 is typically used for the monitoring and protection of the primary side current , which is commonly sensed usin g a current transformer (ct). the input signal at the cs1 pin is fed into an adc for current monito ring. the range of the adc is 0 v to 1.4 v. the input signal is also fed into a comparator for pulse - by - pulse ocp protection. the typical configuration for t he cs1 current sense is shown in figure 14. cs1 1k? 10? i = 100ma i = 10a v in outa outb outc outd adc 12 bits v ref fast ocp 1:100 1v 1 1012-010 figure 14 . current sense 1 (cs1) operation the cs1 adc is used to measure the average value of the primary current ; the reading is averaged eve ry 2.62 ms in an asynchronous fashion to make fault decision s. the adp1046a also writes the 12 - bit cs1 reading every 10 ms to register 0x13. the fast ocp comparator is used to limit the instantaneous primary cu rrent within each switching cycle and has a nominal threshold of 1.2 v. various thresholds and limits can be set for cs1, as described in the current sense and current limit registers section. cs2 operatio n (cs2+, cs2?) cs2+ and cs2? are differential inputs used for the monitoring and protection of the secondary side current. the full - scale range of the cs2 adc is programmable to 60 mv or 120 mv. the differential inputs are fed into an adc through a pair of external resistors that provide the necessary level shifting. the device pins, cs2+ and cs2?, are internally regulated to approxi - mately 1 v by internal current sources. when using low - side current sensing, the current sources are 200 a; therefore, the required resistor value is 1 v/200 a = 5 k. when using high - side current sens ing, the current sources are 2 ma; therefore, the resistor value required is (v out ? 1 v)/2 ma. in the case of v out = 12 v, the required resistor value i s 5.5 k. typical co nfigurations are shown in figure 15 and figure 16. various thresholds and limits can be set for cs2, such as ocp. these thresholds and limits are described in the current sense and current limit registers s ection. cs2+ cs2? adc 12 bits 5k? 5k? 1v i 200a 200a 1 1012-012 figure 15 . low - side resistive current sense (recommended) cs2? cs2+ adc 12 bits 5.5k? 5.5k? 1v i 12v 2ma 2ma 1 1012-0 1 1 figure 16 . high - side resistive current sense when the cs2+ and cs2 ? inputs are not in use, connect the m directly to pgnd, and set cs2 to high - side current sense mode (register 0x27 [2] = 1 ). the cs2 adc is used to measure the cs2 current; the reading is averaged every 2.62 ms in an asynchronous fashion. this averaged rea ding is used to make fault decision s , such as the cs2 ocp fault. the adp1046a also writes the 12- bit cs2 reading every 10 ms to register 0x18. adp1046a data sheet rev. 0 | page 16 of 88 voltage sense and co ntrol loop multiple voltage sense inputs on t he adp1046a are used for the monitoring, control, and protection of the power supply output. this information is available through the i 2 c interface. all voltage sense points can be calibrated digitally to mini mize errors due to external components. this calibration can be performed in the production environment, and the settings can be stored in the eeprom of the adp1046a (see the power supply calibration and trim s ection for more information). for voltage monitoring, the vs1 , vs2 , and vs3 voltage value registers (register 0x15, register 0x16, and register 0x17, respectively ) are updated every 10 ms. the adp1046a stores every adc sample for 10 ms and then outputs the average value at the end of the 10 ms period. therefore, if these registers are read at least every 10 ms , a true average value is read. the adp1046a uses two separate sensing points: vs1 and vs3, depending on the condition of the orfet . w hen the orfet is turned off , the control loop is regulate d via vs1 ; when the orfet is turned on, the control loop is regulated via the di fferential sensing on vs3. this sensing mechanism effectively performs a local and remote voltage sense. the control loop of the adp1046a features a patented multi - path architecture . t he output voltage is conv erted simultaneously by two adcs : a high accuracy adc and a high speed adc . the complete signal is reconstructed and processed in the digital filter to provide a high performance , cost competitive solution. vs1 vs3+ vs3? vs2 adc pgnd vs3 vs2 12 bits vs1 12 bits digital filter 1v 1v 12v 12v 11k? 1k? 1v load 11k? 11k? 1k? 1k? 12v hf adc adc vs3 12 bits adc 1 1012-013 figure 17 . voltage sen se configuration adc s two kinds of - adc s are used in the feedback loop of the adp1046a : a low frequency (lf) adc that run s at 1.56 mh z and a high frequency (hf) adc that runs at 25 mhz. - adcs have a reso lution of one bit and operate differently from traditional flash adcs. the equivalent resolution that can be obtain ed depends on how long the output bit stream of the - adc is sampled. - adc s also differ from nyquist rate adcs in that the quan - tization noise is not uniform across the frequency spectrum. at lower frequencies, the noise is lower, and at higher frequencies, the noise is higher (see figure 18 ) . magnitude frequency nyquist adc noise - adc noise 1 1012-014 figure 18 . noise performance for nyquist rat e and - adcs the low frequency adc runs at approximately 1.56 mhz. for a specified bandwidth, the equivalent resolution can be calculated as follows: ln(1.56 mhz/ bw )/ ln ( 2 ) = n bits for example, at a bandwidth of 95 hz, the equivalent re solution/noise is ln (1.5 6 mhz/95)/ln ( 2 ) = 14 bits at a bandwidth of 1.5 khz, the equivalent re solution/noise is ln(1.56 mhz/1.5 khz)/ln ( 2 ) = 10 bits the high frequency adc has a clock of 25 mhz . i t is comb filtered and outputs at the switching frequency ( f sw ) into the digital fil ter. the equivalent resolution at some sample frequenc ies is listed in table 5 . table 5 . equivalent resolutions for h igh f requency adc at various switching frequencies f sw (khz) h igh frequency adc resoluti on 48.8 9 bits 97.7 8 bits 195.3 7 bits 390.6 6 bits the hf adc has a range of 30 mv. using a base switching frequency (f sw ) of 100 khz (8 - bit hf adc resolution), when f sw increases to 200 khz (7 - bit hf adc resolution), the quantization noise is 0.93 75 mv ( 1 lsb). increasing f sw to 400 khz increases the quantization noise to 3.75 mv ( 1 lsb = 2 30 mv/2 6 = 0.9375 mv ) . vs1 operation (vs1) vs1 is used for the monitoring and protection of the power supply voltage at the output of the lc stage, upstream o f the orfet. the vs1 sense point on the power rail needs an external resistor divider to bring the nominal input voltage to 1 v at the vs1 pin (see figure 17 ). the resistor divider is necessary because the vs1 adc input range is 0 v to 1.6 v (12 - bit reading). this divided - down signal is internally fed into a l ow speed - adc. the output of the vs1 adc goes to the digital filter and is also updated in register 0x15 every 10 ms. the vs1 signal is referenced to pgnd. when the orfet is turned off, the power supply is regulated from the vs1 sense point instead of t he vs3 sense point. data sheet adp1046a rev. 0 | page 17 of 88 vs2 operation (vs2) vs2 is used in conjunction with vs1 to control the orfet gate drive turn - on. the vs2 sense point on the power rail needs an external resistor divider to bring the nominal common - mode signal to 1 v at the vs2 pin (se e figure 17 ). the resistor divider is necessary because the vs2 adc input range is 0 v to 1.6 v . this divided - down signal is internally fed into the vs2 adc. the output of the vs2 adc goes to the vs2 voltage value register (register 0x16). the vs2 signal is never used for the control loop but is used to control the turn - on and turn - off of the orfet (see the or fet control (gate pin) section ) as well as the voltage continuity flag. if the orfet function of the adp1046a is not used, it is recommended that the vs2 input be connected directly to pgnd. the vs2 value is updated in register 0x16 every 10 ms. vs3 oper ation (vs3+, vs3?) vs3 is used for the monitoring and protection of the remote load voltage. vs3 is a fully differential input that is the main feedback sense point for the power supply control loop. the vs3 sense point on the power rail needs an extern al resistor divider to bring the nominal common - mode signal to 1 v at t he vs3 pins (see figure 17 ). the resistor divider is necessary because the vs3 adc input range is 0 v to 1.6 v. this divided - down signal is i nternally fed into a high frequency (hf) adc. the output of the vs3 adc goes to the digital filter and is also updated in register 0x17 every 10 ms. th e hf adc is also the high frequency feedback loop for the power supply . voltage line feedf orward and acsn s the adp1046a supports voltage line feed forward control to improve line transient performance. the acsns value is used to divide the output of the digital filter, and the result is fed in to the pwm engine. the input voltage signal can be sensed at the secondary winding of the isolation transformer and must be filtered by an rcd network to eliminate the voltage spike at the switch node (see figure 19) . acsns adc 0v to 1.6v acsns feedforward adc 0.6v to 1.6v programmable action (reg 0x0d[3:0]) feedforward gain (reg 0x75[1:0]) dpwm engine digital filter acsns gain trim (reg 0x5e) 0.45v 1/x vx r1 r2 from secondary winding r 1 1012-015 figure 19 . feedforward configuration the acsns voltage must be set to 1 v when the nominal input voltage is applied. the acsns adc sampling period is 10 s ; therefore, the decision to modify the pwm output s based on input voltage is performed at t his rate. the feedforward scheme modifies the modulation value based on the acsns voltage. when the acsns input is 1 v, the line feedforward has no effect . for example, if the digital filter output remains unchanged and the acsns voltage changes to 50% of its original value (still higher than 0.5 v), the modulation of the falling edge of outx doubles and vice versa (see figure 20 ). the voltage line feedforward function is optional and is programmable using register 0x75. acsns digital filter output outx t modulation t s t s t modulation 1 1012-016 figure 20 . feedforward control on modulation the acsns level comparator is also connected on the same pin and flags an acsns fault when the voltage on the pin is below 0.45 v within each switching period. the acsns level co mparator is used to detect whether the node is switching. digital filter the loop response of the power supply can be changed using the internal programmable digital filter. a type 3 filter architecture has been implemented. to tailor the loop response to the specific application, the low frequency gain, zero location, pole location, and high frequency gain can all be set individually (see the digital filter programming registers section). it is recommended that the analog devices, inc., software gui be used to program the filter. the software gui displays the filter response in bode plot format and can be used to calculate all stability criteria for the power supply. from the sensed voltage to the duty cycle, the tr ansfer function of the filter in z - domain is as follows: ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? = a z b z c z z m d h(z) 68 . 7 1 24 . 202 where: a = filter_pole_register_value/256. b = filter_zero_register_value/256. c = high_frequency_gain_register_value. d = low_frequency_gain_register_value. m = 1 when 48.8 kh z f sw < 97.7 khz. m = 2 when 97.7 khz f sw < 195.3 khz. m = 4 when 195.3 khz f sw < 390.6 khz. m = 8 when 390.6 khz f sw . f sw is the switching frequency. adp1046a data sheet rev. 0 | page 18 of 88 to transfer the z - domain value to the s - domain, plug the follow - ing bilinear transformation equat ion into the h(z) equation: s f s f z(s) sw sw ? + = 2 2 the digital filter introduces an extra phase delay element into the control loop. the digital filter circuit sends the duty cycle information to the pwm circuit at the beginning of each switch - ing cycle (u nlike an analog controller, which makes decisions on the duty cycle information continuously). therefore, the extra phase delay for phas e margin, , introduced by the filter block is = 360 ( f c / f sw ) where: f c is the crossover frequency. f sw is the switching frequency. at one - tenth the switching frequency, the phase delay is 36. the gui incorporates this phase delay into its calculation s. note that the gui does not account for other delays such as gate driver and propagation delays. two sets of registers allow for two distinct filter responses. the main filter, called the normal mode filter, is controlled by programming register 0x60 to register 0x63. the light load mode filter is controlled by programming register 0x64 to register 0x67. the adp1046a uses the light load mode filter only when the output current measured on cs2 is below the lo ad current threshold (programmed using register 0x3b[2:0]). the analog devices software gui allows the user to program the light load mode filter in the same manner as the normal mode filter. it is recommended that the gui be used for this purpose. in addi tion, during the soft start process , a soft start filter can be used in combination with the normal mode filter and the light load mode filter. the soft start filter is programmed using register 0x71 to register 0x74 . for more information, see the soft start section. filter transitions to avoid output voltage glitches and provide a seamless transition from one filter to another , the adp1046a supports programmable filter transitions . t his feature allows a gradual transition from one filter to another. filter transitions are programmed using register 0x7a[2:0]. pwm and sync hronous rect ifier outputs (outa, outb, outc, o utd, outaux, sr1, sr 2) the pwm and sr outputs are used for control of the primary side drivers and the synchronous rectifier drivers. these outputs can be used for several control topologies such as full - bridge, phase - shifted zvs configurations and interleaved , two switch forward converter configurations. dela ys between rising and falling edges can be individually programmed. special ca re must be taken to avoid shoot - through and cross - conduction. it is recommended that the analog devices software gui be used to program these outputs. figure 21 shows an example configuration to drive a full - bridge, phase - shift ed topology with synchronous rectification. isolator driver driver outa outb outc outd sr1 sr2 v in outa outd outc outb sr1 sr2 1 1012- 1 17 figure 21 . pwm pin assignment for full - bridge, phase - shifted topology with synchronous rect ification the pwm and sr outputs are all synchronized with each other. therefore, when reprogramming more than one of these outputs, it is important to first update all the registers and then latch the information into the adp1046a at the same time. during reprogram ming, the outputs are temporarily disabled. a special instruction is sent to the adp1046a to ensure that new timing information is programmed simultaneou s ly. this is done by setting bit 1 in register 0x7f. it is recommended that pwm outputs be disabled when not in use. outaux is an additional pwm output pin. outaux allows an extra pwm signal to be generated at a different frequency from the other six pwm o utputs. this signal can be used to drive an extra power converter stage, such as a buck controller located in front of a full - bridge converter. outaux can also be used as a clock reference signal. for more information about the various programmable switc hing frequencies and pwm timings, s ee the pwm and synchronous rectifier timing registers section (register 0x3f to register 0x5c). data sheet adp1046a rev. 0 | page 19 of 88 synchronous rectific ation sr1 and sr2 are recommended for use as the pwm control signals when using synchronous rectification. these pwm signals can be configured much like the other pwm outputs. an optional soft start can be applied to the synchronous rectifier pwm outputs . the sr soft start can be programmed using register 0x54[1:0]. ? when sr soft start is disabled (register 0x54[0] = 0), the sr signals are turned on to their full pwm duty cycle value s immediately. ? when sr soft start is enabled (register 0x54[0] = 1) , the sr signals ramp up from zero duty cycle to the desired duty cyc le in steps o f 40 ns per switching cycle. the advantage of ramping the sr signals is to minimize the output voltage step that occur s when the sr fets are turned on without a soft start. the advantage of turning the sr signals completely on immediately is that they can help to minimize the voltage transient caused by a load step. using register 0x54[1], the sr soft start can b e programmed to occur only once ( the first time that the sr signals are enabled ) or every time that the sr signals are enabled, for e xample, when the system enters or exits light load mode. w hen programming the adp1046a to use sr soft start, ensure correct operation of this function by setting the falling edge of sr1 (t 10 ) to a lower value t han the rising edge of sr1 (t 9 ) and by setting the falling edge of sr2 (t 12 ) to a lower value than the rising edge of sr2 (t 11 ). sr soft start can also be disabled by setting register 0x0f[7] = 1 . synchronous rectifie r (sr ) delay the adp1046a is well suited for dc - to - dc converters in isolated topologies. every time a pwm signal crosses the isolation barrier an additional propagation delay is added due to the isolating components. the adp1046a allows programming of an adjust - able delay (0 ns to 315 ns in steps of 5 ns) using register 0x79[5:0]. this delay moves both sr1 and sr2 later in time to compensate for the added delay due to the isolating components (see figure 57 ). in this way, the edges of all pwm outputs can be aligned, and the sr delay can be applied separately as a constant dead time. light load mode the adp1046a can be configured to disable pwm outputs under light load conditions based on the value of cs2. register 0x3b and register 0x7d are used to program the light load mode thresholds for turn - off and turn - on of sr1 , sr2 , and other pwm outputs. below the light load th reshold programmed in register 0x3b , the sr outputs are disabled ; the user can also program any of the other pwm outputs to shut down below th is threshold. light load mode allows the adp1046a to be used with in terleaved topologies that incorporat e automatic phase s hedding at light load. to prevent the system from oscillating between light load and normal mode s due to the thresholds being programmed too close to each other, a programmable debounce is provided in register 0x7d[5:4]. this debounce prevents the part from changing state within the programmed interval. the speed of the sr enable is programmable from 37.5 s to 3 00 s in four discrete steps using register 0x7d[3:2] . this ensures that, in case of a load step, the sr signals (and any other pwm outputs that are temporarily disabled) can be turned on quickly enough to prevent damage to the fets that they are controlling. the light load mode digital filter is also used during light load mode. modulation lim it the modulation limit register (register 0x2e) can be programmed to apply a maximum duty cycle modulation limit to any pwm signal , thus limiting the modulation range of any pwm output . when modulation is enabled, t he maximum modulation limit is applied t o all pwm output s collectively . as shown in figure 22, this limit is the maximum time variation for the modulated edges from the default timing, following the configured modulation direction. there is no minimum du ty cycle limit setting. there - fore, the user must set the rising edges and falling edges based on the case with the least modulation. outx t modulation_limit t rx t fx 1 1012- 1 18 figure 22 . modulation limit settings each lsb in register 0x2e corresponds to a different time step size , depending on the switching frequency (s ee table 46) . the modulated edges cannot extend beyond one switching cycle. the gui provided with the adp1046a is reco mmended for programming this feature (see figure 23). 1 1012- 1 19 figure 23 . setting modulation limits (modulation range shown by arrows) adp1046a data sheet rev. 0 | page 20 of 88 soft start the turning on and off of the adp1046a is controlled by the hardware pson pin and/or the software pson register, depending on the configured settings in register 0x2c. when the user turns on the power supply (enables pson), the following soft start procedur e occurs (see figure 24). 1. the pson signal is enabled at t ime t 0 . if the part is programmed to be always on ( register 0x2c [7:6] = 00), pson is enabled as soon as vcore is above uvlo. 2. the adp1046a waits for the programmed ps_on delay ( set in register 0x2c [4:3] ) . 3. the soft start begins to ramp up the internal digital reference . t he total duration of the soft start ramp is programmable from 5 ms to 100 ms using register 0x5f[7:5]. 4. if the sof t start from precharge function is enabled ( register 0x5f[4] = 1 ), the soft start ramp starts from the value of the output voltage sensed on vs1 or vs3 ( depending on the orfet status ), and t he soft start ramp time is reduced proportionally. if the soft s tart from pre - charge function is disabled , the soft start ramp time is the programmed value in register 0x5f[7:5]. 5. when the power supply voltage exceeds the vs1 under - voltage protection (uvp) limit ( set in register 0x34 [ 6:0]), the uvp flag is reset. 6. the or fet is turned on as soon as the orfet enable thresh - old is met . ( t he orfet enable threshold is programmed in register 0x30[6:5] .) t he regulation point is switched from vs1 to vs3. 7. i f no other fault conditions are present , the pgood x signals wait for the p rogrammed debounce time ( set in register 0x2d[7:4]) and are then enabled. the soft start flag must be unmasked in register 0x7b and register 0x7c (bit 7 must be set to 0). 8. if no orfet is used, the power supply must be configured to regulate using vs3 at a ll times (register 0x33[2] = 1 ). vs2 can be used a s a secondary ovp mechanism. fault condition during soft start if a fault condition occurs during soft start , the controller responds as programmed unless the flag is blanked . flag blanking during soft star t is programmed in register 0x0f. the acsns flag i s always blanked during soft start. the otp, flagin, ovp, and ocp f ault flags can be blanked during soft start by setting the appropriate bits in register 0x0f . the uvp fault is blanked only for the debounc e time during soft start . t herefore, if the soft start period exceeds the debounce time, the uvp fault is triggered and stored in the first flag id register (register 0x10). a read of the latched fault registers and the first flag id register clears the fa lsely triggered uvp condition. digital compensation filters during soft start the adp1046a has a dedicated soft start filter (ssf) that can be used to fine - tune and optimize the dynamic response during the outp ut volt age ramp - up . b efore it ramp s up the internal reference after the pson signal is enabled , the adp1046a evaluates whether the o rfet should be turned on or off by looking at the difference between vs1 and v s2. t his step is done to de termin e whether the regulation point should be vs1 or vs3 (see figure 24) . ? if the regulation point is vs1, the soft start filter is used by default during the ramp - up. at the end of the soft start ramp , the part switches to the normal mode filter (nmf). ? if the regulation point is vs3, the part starts the ramp usin g the normal mode filter (nmf). in both cases, after the voltage reache s 12.5% of the nominal output voltage value, the load current is ev alu ated. ? if th e load current is below the light load mode threshold, the part sw it ches to the light load mode filter (llf). ? if the load current is above the light load mode threshold , the normal mode filter is used until the end of the soft start ramp , even i f the system subsequently enters light load mode based on a change to the load current. register 0x2c can be programmed to configure the use o f the different filters during soft start as follows: ? force s oft s tart f ilter ( bit 0 ) . this option forces the part to use the soft start filter even when the regulation point is vs3 . i n some cases , this option allow s better fine - tuning of the ramp - up voltage. this option can also be selected when an orfet is not used. ? disable l ight l oad m ode d uring s oft s tart ( bit 1) . this option prevents the use of the light load mode filter during soft start, even if the light load condition is met . th e light load mode filter is available for use after the end of the soft start ramp. data sheet adp1046a rev. 0 | page 21 of 88 orfet enable uvp t 0 pson vs3 vs1 (vs1 ? vs2) voltage orfet gate loop controlled from vs1 loop controlled from vs3 uvp flag pgood1 ps_on delay (reg 0x2c[4:3]) ramp time (reg 0x5f[7:5]) pgood debounce (reg 0x2d) 1 1012-120 figure 24 . soft star t timing diagram pson v out ramp time (reg 0x5f[7:5]) 12.5% ref light load filter (llf) normal mode filter (nmf) or soft start filter (ssf) normal mode filter (nmf) or soft start filter (ssf) llf or nmf based on load llf or nmf based on load 11012-121 normal mode filter (nmf) or soft start filter (ssf) figure 25 . filter s equencing at s tartu p adp1046a data sheet rev. 0 | page 22 of 88 or fet control (gate pin ) the gate control signal drives an external orfet. the orfet is used in redundant systems to protect against power flow into the power supply fro m the output terminals of another supply . this ensures that power flows only out of the power supply and that the unit can be hot - swapped. the gate pin is a totem - pole output and does not require a pull - up resistor. the gate pin polarity can be programmed via register 0x2d[1] to be active high or active low. the gate out - put is cmos level (0 v to 3.3 v). an external driver is required to turn the orfet on or off. orfet turn - on the turn - on process for the orfet is controlled by the voltage difference betwee n vs1 and vs2. for this reason, the vs1 and vs2 readings must be correctly calibrated for the orfet func - tion to perform properly . the orfet turn - on circuit detects the voltage difference between vs1 and vs2 (see fi gure 26 ). when the forward voltage drop from vs1 to vs2 is greater than the programmable orfet enable threshold set in register 0x30[6:5], the orfet is enabled. the orfet enable threshold can be set to 0 % , ?0.5%, ?1%, or ?2% of the nominal output voltage. orfet turn - off the orfet can be turned off by three methods: ? fault f lag. any f lag in a f ault c onfiguration r egister (register 0x08 to register 0x0d) can be programmed with an action to turn off the orfet. the orfet is kept off for as long as the flag is set. ? orfet p rogrammable c omparator. if the reverse voltage present on cs2 exceeds the analog comparator threshold programmed in register 0x30[4:2] , the orfet is turned off . this comparator can be disabled using register 0x30[0] . ? gate s ignal d isable. when register 0x5d[0] = 1 , the gate signal is disabled and has no effect on the vsx feedback point . orfet gate control and regulation points the gate signal is enabled when the threshold configured in register 0x30[6:5]) is met. the gate signal controls a very important function of output voltage regulation: the control loop sensing point. ? when the gate signal is disabled, the orfet is turned off and the voltage regulation sensing point is vs1. ? when the gate si gnal is enabled, the orfet is turned on and the voltage re gulation sensing point is vs3. recommended setup for a 12 v application i n normal operating mode, follow this procedure: ? when 12 v < v out < ovp, use the fast orfet control circuit to turn off the o rf e t. ? when v out > ovp, use load ovp to turn off the orfet. in light load mode, follow this procedure: ? when 12 v < v out < ovp, use acsns to turn off the orf e t. ? when v out > ovp, use load ovp to turn off the orfet. in a 12 v application, when an internal shor t circuit occurs, use cs1 ocp or vs1 uvp to shut down the unit and restart it. fast orfet comparator fast orfet threshold orfet disable cs2? cs2+ 12v n ? n ? n ? n ? v out vs2 vs1 r sense gate fast orfet bypass fast orfet debounce s r q orfet enable orfet enable threshold flags driver debounce gate disable 1 1012-122 figure 26 . orfet control circuit detailed internal diagram data sheet adp1046a rev. 0 | page 23 of 88 orfet operation examples hot plug into a live bus a new psu is plugged into a live 12 v bus (yellow). the internal voltage, vs1 (red), is ramped up before the orfet is turned on. after the orfet is turned on (green), current in the new psu begins to flow to the load (blue). the turn - on voltage threshold between the new psu and the bus is pro grammable. ch2 2.00v ch4 10.0v ch1 2.00v ch3 2.00a m10.0ms a ch4 100mv 2 3 4 cs2 vs3 vs1 orfet 1 1012-017 figure 27 . hot plug into a live bus (yellow is bus voltage; red is vs1 voltage; green is orfet control signal; blue is load current) runaway master a rogue psu on the bus (yellow) has a fault condition, causing the bus voltage to increase above the ovp threshold. the good psu turns off the orfet (green) and regulates its internal volt - age , vs1 (red). when the rogue power supply fault condition is removed, the bus voltage decreases. the orfet of the good psu is immediate ly turned on , and the good psu resumes regulating from vs3. ch2 2.00v ch4 10.0v ch1 2.00v ch3 2.00a m50.0ms a ch4 0mv 3 4 cs2 vs3 vs1 orfet 1 1012-018 figure 28 . runaway master (yellow is b us voltage; red is vs1 voltage; green is orfet control signal; blue is load current) short circuit when one of the output re ctifiers fails, the bus voltage can collapse if the orfet is not promptly turned off. the fast orfet comparator is used to protect the system from this fault event. figure 29 shows a short circuit applied to the ou tput capacitors before the orfet. after the fast orfet threshold for cs2 (blue) is triggered, the orfet (green) is turned off. figure 29 also shows the operation when the short circuit is removed. the internal reg ulation point, vs1 (red), returns to 12 v, and the orfet (green) is reenabled. the psu again begins to contribute current to the load (blue). ch2 2.00v ch4 10.0v ch1 2.00v ch3 2.00a m200.0ms a ch4 7.5mv 3 4 cs2 vs3 orfet vs1 1 1012-019 figure 29 . internal short circuit (yellow is bus voltage; red is vs1 voltage; green is orfet control signal; blue is load current) light load mode operation psu 1 increases its voltage at light load from 12 v to 12.1 v (yellow). both psu 1 and psu 2 are ccm ; therefore psu 1 sources current and psu 2 sinks current (blue). in psu 2, the orfet control turns off the orfet to prevent reverse current from flowing. note that the orfet voltage (green) is solid during this transition because psu 1 and psu 2 are in ccm mode. ch2 2.00v ch4 10.0v ch1 2.00v ch3 2.00a m5.0ms a ch4 8.3mv 3 4 cs2 vs3 orfet vs1 1 1012-020 figure 30 . light load mode (yellow is bus voltage; red is vs1 voltage; green is orfet control signal; blue is load current) adp1046a data sheet rev. 0 | page 24 of 88 vdd when vdd is applied, a certain time elapses before the part is capable of regulating the power supply. when vdd rises above the power - on reset and uvlo levels, it takes approx imately 20 s for vcore to reach its operational point of 2.5 v. t h e eeprom contents are then downloaded to the registers. the download takes an additional 25 s (approximately). after the eeprom download, the a dp1046a is ready for operation. if the adp1046a is programmed to power up at this time (pson is enabled), the soft start ramp begins. otherwise, the part waits for the pson signal. the p roper amount of decoupl ing capacitance must be placed between vdd and agnd, as c lose as possible to the device to minimiz e the trace length. it is recommended that the vcore pin not be used as a reference or to generate other logic levels using resistive dividers. vdd/vcore ovlo the adp1046a has built - in overvoltage protection (ovp) on its supply rails. when the vdd or vcore voltage rises above the ovlo threshold, the response can be programmed using register 0x0e[7:5]. it is recomme nded that when a vdd/ vcore ov p fault occurs , the response be set to download the eeprom before restarting the part (set register 0x0e[6] = 1). power good the adp1046a has two open - drain power - good pins . the pg ood1 pin is driven low when a pgood1 fault condition is present; the pgood2 pin is driven low when a pgood2 fault condition is present. the pgood1 and pgood2 pins and flags can be programmed to respond to the following flags: ? soft start ? cs1 fast ocp ? cs1 accurate ocp ? cs2 accurate ocp ? uvp ? local ovp (fast and accurate) ? load ovp ? orfet (gate pin) the masking of these flags is programmed in register 0x7b (for pgood1) and register 0x7c (for pgood2) . w hen a flag is masked, it does not set pgood1 or pgood2. the following additional flags can also set the pgood2 pin either unconditionally or based on the flag response , as programmed in register 0x2d[3] ( see figure 31 and table 45). ? voltage continuity ? orfet disable ? acsns ? external f lag (flagin pin) ? otp t hese additional flags can be programmed in register 0x2d[3] to always set pgood2 or to set pgood2 only if the flag action is not set to ignore in the fault configuration register for that flag (see table 12 and table 13). pgood1 (flag and pin) pgood2 (flag and pin) additional flags -voltage continuity -orfet disable -acsns -flagin -otp masked by reg 0x7b masked by reg 0x7c debounce (reg 0x2d[7:6]) debounce (reg 0x2d[5:4]) main flags -soft start -cs1 fast ocp -cs1 accurate ocp -cs2 accurate ocp -uvp -local ovp (fast and accurate) -load ovp -orfet (gate pin) if reg 0x2d[3] = 0, the additional flags always affect pgood2, regardless of the programmed action. if reg 0x2d[3] = 1, the additional flags affect pgood2 only if they are not set to be ignored. 1 1012-127 figure 31 . pgood1, pgood2 programming data sheet adp1046a rev. 0 | page 25 of 88 current sharing the adp1046a supports both analog current sharing and digital current sharing. t he adp1046a use s the cs2 current information for current sharing ( this setting is programmed in register 0x29[3]) . analog current sharing a nalog current sharing uses t he internal current sensing circuitry to provide a current reading to an external current error amplifier . therefore, an additional differential current amplifier is not necessary. the current reading from cs2 c an be output to the shareo pin in the form of a digital bit stream, which is the output of the current sense adc (see figure 33 ). the bit stream from the - adc is proportional to the current delivered by this unit to the load. by filtering this digital bit stream using an external rc filter, the current information is turned into an analog voltage that is proportional to the current delivered by this unit to the load. this voltage can be compared to the share bus voltage. if the unit is not supplying enough current, an error signal can be applied to the vs3 feedback point. this signal causes the unit to increase its output voltage and , in turn , its curren t contribution to the load. digital share bus the digital share bus scheme is similar in principle to the tradi - tional analog share bus scheme. the difference is that instead of using a voltage on the share bus to represent current, a digital word is used. the adp1046a outputs a digital word onto the share bus. the digital word is a function of the current that the power supply is providing (the higher the current, the larger the digital word). the power supply with the highest current controls the bus (master). a power supply that is putting out less current (slave) sees that another supply is providing more power to the load than it is. during the next cycle, the slave increases its current output contri - butio n by increasing its output voltage. this cycle continues until the slave outputs the same current as the master, within a pro - grammable tolerance range. figure 32 shows the configuration of the digital share bus. digital word share bus current sense info sharei shareo power supply a digital word current sense info sharei shareo power supply b v dd 1 1012-023 figure 32 . digital current share configuration the digital share bus is based on a single - wire communication bus principle; that is, the clock and data signals are contained together. when two or more adp1046a devices are connected, they syn - chronize their share bus timing. this synchronization is performed by the start bit at the beginning of a communications frame. if a new adp1046a is hot - swapped onto an existing digital share bus, the device waits to begin sharing until the next frame. the new adp1046a monitors the share bus until it sees a stop bit, which designates the end of a share frame. it then performs synchronization with the other adp1046a devices during the next start bit. the digital share bus frame is shown in figure 34. current sense adc share bus lpf bit stream bit stream shareo voltage current cs2? cs2+ 1 1012-222 figure 33 . analog current share configuration 8-bit data previous frame start bit 0 2 stop bits (idle) start bit 0 2 stop bits (idle) next frame frame 1 1012-024 figure 34 . digital current share frame timing diagram adp1046a data sheet rev. 0 | page 26 of 88 figure 35 shows the possible signals on the share bus. logic 1 logic 0 idle previous bit next bit t 1 t 0 t bit 1 1012-025 figure 35 . share bus high, low, and idle bits the length of a bit (t bit ) is fixed at 10 s. a logic 1 is defined as a high - to - low transition at the start of the bit and a low - to - high transition at 75% of t bit . a logic 0 is defined as a high - to - low trans ition at the start of the bit and a low - to - high transition at 25% of t bit . the bus is idle when it is high during the whole period of t bit . all other activity on the bus is illegal. glitches up to t glitch (200 ns) are ignored. the digital word that repres ents the current information is eight bits long. the adp1046a takes the eight msbs of the cs2 read - ing and uses th is reading as the digital word (see figure 36). digita l share bus scheme each power supply compares the digital word that it is outputting with the digital words of all the other supplies on the bus. round 1 in round 1, every supply first places its msb on the bus. if a supply senses that its msb is the sam e as the value on the bus, it continues to round 2. if a supply senses that its msb is less than the value on the bus, it means that this supply must be a slave. when a supply becomes a slave, it stops communicating on the share bus because it knows that it is not the master. the supply then increases its output voltage in an attempt to share more current. if two units have the same msb, they both continue to rou nd 2 because either of them may be the master. round 2 in round 2, all supplies that are still communicating on the bus place their second msb on the share bus. if a supply senses that its msb is less than the value on the bus, it means that this supply must be a slave and it stops communicating on the share bus . round 3 to round 8 the same algorith m is repeated for up to eight rounds to allow supplies to compare their digital words and, in this way, to determine whether each unit is the master or a slave. digital share bus configuration the digital share bus can be configured in various ways. the ba nd - width of the share bus loop is programmable in register 0x29[2:0]. the extent to which a slave tries to match the current of the master is programm able in register 0x2a[3:0]. enable the digital share bus by setting register 0x29[3] to 1 . current sense adc 1 lsb = 29.3v 35mv/29.3v = 1195 master + 35mv ? digital word digital filter 16 12 bits 1195 dec 0x4ab 8 bits 74 dec 0x4a 0x4a sharei cs2+ cs2? v dd share bus 8-bit word 0xb5 8-bit word 0x4a shareo i out = 35a 1m? psu a 1 1012-026 figure 36 . how the share bus generates the digital word to place on the digital share bus data sheet adp1046a rev. 0 | page 27 of 88 power supply system and fault monitoring the adp1046a has extensive system and fault monitoring capabili ties. the system monitoring functions include voltage, current, power, and temperature readings. the fault conditions include out - of - limit values for current, voltage, power, and temperature. the limits for the fault conditions are programmable . the adp1046a has an extensive set of flags that are set when certain programmed thresholds or limits are exceeded. these thresholds and limits are described in the fault registers section . flags the adp1046a has an extensive set of flags that are set when certain limits, conditions, and thresholds are exceeded. the real - time status of these flags can be read in register 0x00 to registe r 0x03. the response to these flags is individually program - mable. flags can be ignored or used to trigger actions such as turning off certain pwm outputs or the orfet gate. flags can also be used to turn off the power supply. the adp1046a can be programmed to respond when these flags are reset. for more information, see the fault registers section . the adp1046a also has a se t of latched fault registers (register 0x04 to register 0x07). the latched fault registers have the same flags as register 0x00 to register 0x03, but the flags in the latched registers remain set so that intermittent faults can be detected. reading a lat ched fault register resets all the flags in that register. monitoring functions the adp1046a monitors and reports several signals, including voltages, currents, power, and temperature. all these values are sto red in separate registers and can be read through the i 2 c interface. for more information, s ee the value registers section. voltage readings the vs1, vs2, and vs3 adcs have an input range of 1.6 v . the outputs of the adcs are 12 - bit values, which means that the lsb size is 1.6 v/4096 = 390.625 v. the user is limited to an input range of 1.4 v, which means that the adc output code is limited to 1.4 v/390.6 v = 3584. the equation to calculate the adc code at a specified voltage (vx) at the pin is given by the following formula: adc code = vx /1.6 4096 for example, when there is 1 v on the input of the adc , adc code = 1 v/1.6 4096 adc code = 2560 in a 12 v application, the 12 v reading is divided down using a resistor divider network to provide 1 v at the sense pin. therefore, to conve rt the register value to a real voltage, use the following formula: v out = ( lsb 2560) (( r1 + r2 )/ r2 ) in a 12 v system, this equates to v out = (390.625 v 2560) (11 k ? + 1 k ? )/1 k ? current readings cs1 pin cs1 has an input range of 1.4 v . the adc performs a 12 - bit reading conversion o f this value, which means that the lsb size is 1.4 v /4096 = 341.8 v. when there is exactly 1 v on the cs1 pin, the val ue in the cs1 value register (register 0x13[15:4]) reads 2926. the equation to calculate the adc code at a specified cs1 input voltage (vx) is given by the following formula: adc code = vx /1.4 4096 for example, when there is 1 v on the cs1 input pin , adc code = 1 v/1.4 4096 adc code = 2926 cs2 +, cs2 ? pin s the full - scale (fs) range for th e cs2 adc can be set to 60 mv or 120 mv using register 0x27[5] . the cs2 adc has an input range of 120 mv. the resolution is 12 bits, which means that the lsb size is 120 mv/4096 = 29.30 v. the user is limited to an i nput range of 110 mv. the equation to calculate the adc code at a specified cs2 input voltage (v x ) is given by the following formula: adc code = v x /(120 mv) 4096 for example, when there is 50 mv on the input of the adc , adc code = 50 mv/120 mv 4096 adc code = 1707 therefore, to convert the cs2 register value to a real current, use the following formula: i out = ( cs2_adc_code /4096) ( fs / r sense ) where: cs2_adc_code is the value in register 0x18[15:4]. fs is the full - scale voltage drop (60 mv or 120 mv) . r sense is the sense resistor v alue. for example, if cs2_adc_code = 1520, r sense = 10 m?, and fs = 120 mv, the real current is calculated as follows: i out = (1520/4096) (120 mv/10 m?) i out = 4.453 a adp1046a data sheet rev. 0 | page 28 of 88 power readings the output power value register (register 0x19) is the product of the vs3 voltage value and the cs2 current value. therefore, a combination of the formulas in the voltage readings section and the cs2+, cs2? pins section is used to calculate the power reading in watts. this register is a 16-bit word. it multiplies two 12-bit numbers and discards the eight lsbs. p out = v out i out for example, p out = 12 v 4.453 a = 53.436 w power monitoring accuracy the adp1046a power monitoring accuracy is specified relative to the full-scale range of the signal that it is measuring. first flag fault id and value registers when the adp1046a registers several fault conditions, it stores the value of the first fault in a dedicated register. for example, if the overtemperature (otp) fault is registered followed by an ovp fault, the otp flag is stored in the first flag id register (register 0x10). this register gives the user more information for fault diagnosis than a simple flag. the contents of this register are latched, meaning that they are stored until read by the user. the contents are also reset by toggling pson. if a flag is set to be ignored, it does not appear in the first flag register. external flag input (flagin pin) the flagin pin can be used to send an external fault signal into the adp1046a . register 0x0a[3:0] can be used to program the flagin flag to trigger an action. temperature readings (rtd pin) the rtd pin is set up for use with an external negative tempera- ture coefficient (ntc) thermistor (see figure 38). the rtd pin has an internal programmable current source. an adc monitors the voltage on the rtd pin. the rtd temperature value register, register 0x1a, is updated every 10 ms. the adp1046a stores every adc sample for 10 ms and then outputs the average value at the end of the 10 ms period. the rtd adc has an input range of 1.6 v and a resolution of 12 bits, which means that the lsb size is 1.6 v/4096 = 390.625 v. the user is limited to an input range of 1.3 v, which means that the maximum adc output code is limited to 1.3 v/390.6 v = 3328. the output of the rtd adc is linearly proportional to the volt- age on the rtd pin. however, thermistors exhibit a nonlinear function of resistance vs. temperature. therefore, the user must perform postprocessing on the rtd adc reading to accurately read the temperature. by connecting an external resistor (r ext ) in parallel with the ntc thermistor (th), a constant current can be used to achieve linear- ization (see figure 37). adc dac rtd th r ext 11012-134 figure 37. temperature measurement using thermistor an internal, precision current source of 10 a, 20 a, 30 a, or 40 a can be selected in register 0x11. this current source can be trimmed by means of an internal dac to compensate for thermistor accuracy (see the rtd/otp trim section). the user can select the size of the output current source using bits[7:6] of register 0x11. the adp1046a implements a linearization scheme based on a preselected combination of external components and current selection for best performance when measuring linearized tem- peratures in degrees celsius in the industrial range. for more information about the required thermistor and selecting and trimming the precision current sources, see the temperature linearization scheme section. optionally, the user can process the rtd reading and perform postprocessing in the form of a lookup table or polynomial equation to match the specific ntc thermistor used. with the internal current source set to 46 a, the equation to calculate the adc code at a specified ntc thermistor value (rx) is given by the following formula: adc code = 46 a rx /1.6 4096 for example, at 60c, the ntc thermistor at the rtd pin is 21.82 k. rtd_adc_code = 46 a 21.82 k/1.6 4096 = 2570 flags otp flag otp threshold reg 0x2f[7:0] rtd temperature value register reg 0x1a[15:4] rtd temperature value in c reg 0x1b[7:0] signal conditioning 10a/20a/30a/40a rtd 100k ? ntc 16.5k ? rtd adc 11012-027 figure 38. rtd pin internal details data sheet adp1046a rev. 0 | page 29 of 88 temperature linearization scheme the adp1046a implements a linearization scheme based on a preselected combination of thermistor (100 k?, 1%), external resistor (16.5 k?, 1%), and the 46 a current source for best performance when linearizing measured temperatures in the industrial range. the required ntc thermistor should have a resistance o f 100 k?, 1%, such as the ncp15wf104f03rc (beta = 4250, 1%). it is recommended that 1% tolerance be used for both the resistor and beta values. reading the linearized temperature reading register 0x1b (updated every 10 ms) returns the current temperature a ccording to an internal linearization scheme . s ee table 1 for the specified accuracy of these measurements . the temperature reading result is represented in 8 - bit decimal format in c; therefore , the tempe ra ture ra nge for this reading is from 0 c to 255 c. overtemperature prot ection (otp) if the temperature sensed at the rtd pin exceeds the threshold programmed in register 0x2f , the otp flag is set. the response to the otp flag is programmable using register 0x0b[7: 4]. an rtd trim is required to make accurate temperature readings at the lower end of the rtd adc range to account for tolerances in the ntc thermistor and the external resistor. this trim results in a more accurate measurement for determining the otp thre shold ( see the rtd/otp trim section). overcurrent protecti on (ocp) the adp1046a has several ocp functions. cs1 and cs2 have separate ocp circuits to provide both primary and secondar y side protection. cs1 ocp cs1 has two protection circuits: cs1 fast ocp and cs1 accurate ocp (see figure 39). cs1 fast ocp cs1 fast ocp is an analog comparator. when the voltage at the cs1 pin e xceeds the (fixed) 1.2 v thresh old, the cs1 fast ocp flag is set. a programmable blanking time can be set to ignore the leading edge current spike at the beginning of the current signal ( leading edge blanking ). a debounce time can be programmed to improve the noise immu - nity of the ocp circuit. when the cs1 fast ocp comparator is set, the outa, outb, outc, and outd pwm outputs are immediately disabled for the remainder of the switching cycle. the se outputs are reenabled at the start of the next switching cycle. this function cannot be bypassed. cs1 accurate ocp cs1 accurate ocp is used for more precise control of over current protection. with cs1 accurate ocp, the reading at the output of the cs1 adc (register 0x13) is compared to a programmable ocp limit. the cs1 accurate ocp value can be programmed from 0 to 31 decimal using register 0x22[4:0]. if the cs1 reading exceeds the cs1 accurate ocp limit, the cs1 accurate ocp flag is set. the cs1 adc is asynchronously sampled, and the readings are averaged every 2.62 ms to make a fau lt decision. the flag response is programmed in register 0x08 . v in outa outd outc outb cs1 cs1 adc 1.2v fast ocp comparator 12 cs1 fast ocp flag pwm cs1 accurate ocp flag cycle-by-cycle shutdown outa outb outc outd sr1 sr2 outaux flags cs1 fast ocp bypass reg 0x27[4] cs1 fast ocp debounce reg 0x27[7:6] cs1 fast ocp blanking reg 0x22[7:5] flagin cs1 accurate ocp setting reg 0x22[4:0] shutdown cycle timeout reg 0x27[1:0] asynchronous 2.62ms averaging 1 1012-135 figure 39 . cs1 ocp detailed internal schematic adp1046a data sheet rev. 0 | page 30 of 88 cs2 accurate ocp setting reg 0x26 cs2? cs2+ 5k? 5k? adc 12 asynchronous 2.62ms averaging programmable debounce and action (reg 0x0e and reg 0x09) 1v 200a 200a 1 1012-136 figure 40 . cs2 ocp detailed internal schematic cs2 ocp cs2 has one ocp protection circu it: cs2 accurate ocp (see figure 40) . the reading at the output of the cs2 adc (register 0x18) is compared to a programmable ocp threshold. the cs2 ocp threshold can be programmed using register 0x26[7:0]. if the cs2 reading excee ds the cs2 ocp threshold, the cs2 accurate ocp flag is set. the cs2 adc is asynchronously sampled , and the readings are averaged every 2.62 ms to make a fault decision. the flag response is programmed in register 0x09 . constant current mod e the adp1046a can be configured to operate in constant current mode. the threshold to enter constant current mode operation is 3% current below the cs2 accurate ocp setting (see figure 41) . below this current, the part operates in constant voltage mode, using the output voltage as the feedback signal for closed - loop operation. ocp v out v out nominal i out 0.97 ocp 1 1012-137 figure 41 . constant current mode (v out vs. i out ) when the adp1046a reaches the constant current mode threshold, a flag is set in register 0x02[4] and in register 0x06[4] (real - time and latched flag registers, respectively). when this flag is set, the cs2 current reading is used to control the output voltage regulation point. the output voltage is ramped down linearly as the load increases to ensure that the current remains constant. the constant current control loop is relatively low bandwidth because the current is averaged over a 328 s peri od. the output voltage changes at a maximum rate of 1.18 v/sec at the vs3 pins; therefore, the instantaneous value of the current can exceed the constant current limit for a very short period of time, depend - ing upon the transient. as the output voltage f alls , the uvp flag (register 0x0b[3:0]) can be use d to program a shutdown action. overvoltage protecti on (ovp) the adp1046a has three separate ovp circuits. if the output voltage at the vs1 pin , vs2 pin , or vs3 pin s exceeds the programmable threshold for that pin, th e appropriate ovp flag is set . the flag response is programmed in register 0x0 9 [3:0] for the vs2 and vs3 ovp flag s or in register 0x0 a [7:4] for the vs1 ovp flag. vs1 has two ovp circuits : a fast com parat or (fast ovp) and an adc - based comparator (accurate ovp). vs2 and vs3 share an accurate ovp circuit. the ovp circuits can be programmed for different ovp thresholds. see register 0x32 and regi ster 0x33 for more information. the sampling time for the a dc - based comparators is 80 s. additional debounce in steps of 80 s can be added using bits[1:0] of register 0x32 and register 0x33 . the fast ovp comparator also has a programmable threshold and debounce time . these values are programmed in register 0x37. data sheet adp1046a rev. 0 | page 31 of 88 undervoltage protection (uvp) if the voltage sensed at the vs1 pin falls below the program- mable uvp threshold, the uvp flag is set. the uvp threshold is programmed in register 0x34; the gui can also be used, as shown in figure 42. the response to the uvp flag is programmable in register 0x0b[3:0]. undervoltage protection and the uvp flag are disabled during soft start. ac sense (acsns) the acsns circuit performs multiple monitoring and control functions. two adcs and a fast comparator are connected to this pin. ? the fast adc is used for the voltage feedforward function (see the voltage line feedforward and acsns section). this adc has an equivalent resolution of 11 bits at 10 s. ? the slow adc is used to report the input voltage. this adc has a resolution of 12 bits at 10 ms. ? the fast comparator is used to monitor whether a switching waveform is present at the output of the synchronous rectifier stage (or rectifier diodes). the pick-off point upstream of the output inductor is connected to the acsns pin through an external rcd divider network. the output of the acsns slow adc is a 12-bit value reported in register 0x14. the gain of this adc can be adjusted using register 0x5e[6:0] to compensate for divider errors and the voltage spike. the equation to calculate the adc code is given by the following formula: adc code = vx /1.6 4096 where vx is the voltage at the acsns pin. for example, when there is 1 v on the input of the adc adc code = 1 v/1.6 4096 adc code = 2560 v sense = ( vx ) ( r1 + r2 )/ r2 where v sense is the filtered secondary voltage. the primary input voltage can be calculated by multiplying v sense by the turns ratio (n1/n2) as follows: v primary = vx ( r1 + r2 )/ r2 (n1/ n2) the acsns comparator threshold is set at 0.45 v. if the average voltage on the acsns pin falls below this threshold, the acsns flag is set in register 0x03[2] and in register 0x07[2] (real-time and latched flag registers, respectively), and the programmed action for the flag is executed. when operating in resonant mode, the acsns comparator is used for the timing of the synchronous rectifiers and, therefore, the additional features of the adc cannot be used. for more information, see the resonant mode operation section. 11012-138 figure 42. voltage sense window in simulation mode ( adp1046a gui) adp1046a data sheet rev. 0 | page 32 of 88 volt-second balance the adp1046a has a dedicated circuit to maintain volt-second balance in the main transformer when operating in full-bridge topology. this circuit eliminates the need for a dc blocking capac- itor. in interleaved topologies, volt-second balance can also be used for current balancing to ensure that each interleaved phase contributes equal power. the circuit monitors the current flowing in both legs of the full- bridge topology and stores this information. it compensates the selected pwm signals to ensure equal current flow in both legs of the full-bridge topology. the input is through the cs1 pin. several switching cycles are required for the circuit to operate effectively. the maximum amount of modulation applied to each edge of the selected pwm outputs is programmable to 80 ns or 160 ns in register 0x28[2]. the volt-second balance settings are programmed in register 0x28 and in register 0x76 through register 0x78. it is recommended that the analog devices software gui be used to program these settings. the compensation of the pwm drive signals is performed on the edges of two selected outputs. the sr1 and sr2 edges can also be independently set to modulate due to the volt-second balance circuit to maintain the timing relation to the primary side signals. digital load line and slew rate the adp1046a can optionally introduce a digital load line into the power supply. this option is programmed in the load line impedance register (register 0x36). two parameters can be configured independently: slew rate and load line value. the slew rate (register 0x36[6:4]) determines how quickly the output voltage is adjusted in response to a change in the digital reference. eight different settings are available. the load line value (register 0x36[2:0]) controls the slope of the load line. the amount of output resistance introduced can be calculated as follows: r out = 0.1 v out_nom cs2 r sense /( cs2 range 2 load_set[2:0] ) where: v out_nom is the nominal output voltage when vs3 = 1 v. cs2 r sense is the sense resistor value. cs2 range is 120 mv or 60 mv. load_set[2:0] is the value of bits[2:0] in register 0x36 (0 to 7 decimal). for example, if v out_nom = 12 v, cs2 r sense = 10 m, cs2 range = 120 mv, and load_set[2:0] = 3, r out = 0.1 12 v 10 m/(120 mv 2 3 ) = 12.5 m this feature can be used for advanced current sharing techniques. by default, the load line is disabled. the load line is introduced digitally by modifying the value of the digital reference based on the cs2 reading. figure 43 and figure 44 show the load line as a percentage of v out vs. the r sense voltage drop. 100 90 91 92 93 94 95 96 97 98 99 0 20 40 60 80 100 120 10 30 50 70 90 110 v out (%) r sense voltage drop (mv) setting 7 setting 6 setting 5 setting 4 setting 3 setting 2 setting 1 setting 0 11012-030 figure 43. load line settings with 120 mv cs2 range 100 88 90 92 94 96 98 0 102030405060 5 1525354555 v out (%) r sense voltage drop (mv) setting 7 setting 6 setting 5 setting 4 setting 3 setting 2 setting 1 setting 0 11012-031 figure 44. load line settings with 60 mv cs2 range data sheet adp1046a rev. 0 | page 33 of 88 power supply calibra tion and trim the adp1046a allows the entire power sup ply to be calibrated and trimmed digitally in the production environment. it can calibrate items such as output voltage and trim for tolerance errors introduced by sense resistors and resistor dividers, as well as its own internal circuitry. the part is fa ctory trimmed, but it can be retrimmed by the user to compensate for the errors intro - duced by external components. the adp1046a gui allows the user to automatically revert the trim settings to the ir factory de fault values. to unlo c k the t rim r egisters for write access , write to the trim _password register ( register 0x 89) . write the trim password twice (the fact ory default password is 0xff). the adp1046a allows the u ser enough trim capability to trim for external components with a tolerance of 0.5% or better. if the adp1046a is not trimmed in the production environment, it is recommended that components with a tolerance of 0.1% or better be used for the inputs to cs1, cs2, vs1, vs2, and vs3 to meet data sheet specifications. cs1 trim using a dc signal a known voltage (vx) is applied at the cs1 pin. the cs1 adc should output a digital code equal to vx/1.4 4096. the cs1 g ain trim register (register 0x21) is adjusted until the cs1 adc value in register 0x13[15:4] reads the correct digital code. using an ac signal a known current (ix) is applied to the psu input. this current passes through a current transformer, a diode rec tifier, and an external resistor (r cs1 ) to convert the current information to a voltage (vx). this voltage is fed into the cs1 pin. the voltage (vx) is calculated as follows: vx = ix ( n1/ n2 ) r cs1 where n1/ n2 is the turns ratio of the current transforme r. the cs1 adc outputs a digital code equal to vx/1.4 4096. the cs1 gain trim register (register 0x21) is adjusted until the cs1 adc value in register 0x13[15:4] reads the correct digital code. cs2 trim the cs2 trim must compensate for offset and gain er rors. the offset error requires both an analog trim and a digital trim. this error inc ludes the mismatch of the level shifting resistors to the input s of the cs2 differential amplifier and the tolerance of the current sense element. cs2 offset trim offset errors can be i ntroduced by the external level shifting resistors and the internal current sources. it is best to use two 0.1% matched resistors or matched resistors within the same package. it is important to perform the cs2 offset trim as described in the following steps: 1. set high - side or low - side c urrent sensing using register 0x27 [2]. 2. set the nominal full - scale sense resistor voltage drop in register 0x27[5] to 1 for the 120 mv range or to 0 for the 60 mv range. 3. apply no - load current across the sens e resistor. 4. set the cs2 gain trim value to 0 ( register 0x23 = 0 ) . 5. set the cs2 digital offset trim value to 0 ( register 0x25 = 0 ) . 6. adjust the cs2 analog offset trim value in register 0x24[6:0] . for the 120 mv range, adjust register 0x24 until the cs2 value in register 0x18[15:4] reads as close to 100 decimal (0x64) as possible; this value must be greater than 50 (0x32). for the 60 mv range, adjust register 0x24 until the cs2 value in register 0x18[15:4] reads as close to 200 decimal (0xc8) as possible; this value must be greater than 100 (0x64). 7. adjust the cs2 digital offset trim value in register 0x25 until the cs2 value in register 0x18[15:4] reads 0 . the offset trim is now completed, and the adc code reads 0 when there is a no - load current across the sens e resistor. cs2 gain trim after performing the offset trim, perform the gain trim to remove any mismatch that is introduced by the sense resistor tolerance. the adp1046a can trim for sense resistors with a tole rance of 1% or better. 1. apply a known load current (i out ) across the sense resistor. 2. adjust the cs2 gain trim value in register 0x23[5:0] until the cs2 value in r egister 0x18[15:4] reads the value calculated by the following formula: cs2 value = i out r se nse / fs 4096 where: fs is the full - scale voltage drop (120 mv or 60 mv) . r sense is the sense resistor value. i f cs2 is programmed to the 120 mv range and i out = 10 a, r sense = 10 m, and fs = 120 m v, cs2 value = (10 a 10 m)/120 mv 4096 cs2 value = 3 413 decimal if cs2 is programmed to the 60 mv range and i out = 5 a, r sense = 5 m, and fs = 60 m v, cs2 value = (5 a 5 m)/60 mv 4096 cs2 value = 1707 decimal the cs2 circuit is now trimmed. the ocp limits and settings should be configured after the c urrent sense trim is performed. adp1046a data sheet rev. 0 | page 34 of 88 voltage calibration and trim the voltage sense inputs are optimized for sensing signals at 1 v (t he usable input range is 1.4 v ) . in a 12 v system, a 12:1 resistor divider is required to reduce the 12 v signal to below 1. 4 v. it is recommended that the output voltage of the power supply be reduced to 1 v at this pin for best performance. the tolerance of the resistor divider introduces errors that need to be trimmed. the adp1046 a has enough trim range to trim out errors introduced by resistors with a tolerance of 0.5% or better. the vs1, vs2, and vs3 adcs produce a digital code equal to vsx/1.6 4096. the adcs output a digital word of 2560 decimal (0xa00) in bits[15:4] of regis ter 0x15, register 0x1 6 , and register 0x1 7 when there is exactly 1 v at their inputs. output voltage set ting (vs3+, vs3? tri m) the vs3 input s require a gain trim. set the output regulation point to 100% o f the nominal value (register 0x31 = 0x a0). enable the power supply with no - load current. the power supply output voltage is divided down by the vs3 resist or divider to give 1 v across the vs3+ and vs3? differential input pins. the vs3 trim register (register 0x3a) is adjusted until the output voltage is at the desired value. this step should be performed before any other trim routine. the vs3 voltage valu e in register 0x17[15:4] reads 2560 decimal (0xa00). vs1 trim the vs1 input requires a gain trim. enable the power supply with no - load current. it is recommended that the vs1 voltage be divided down by the vs1 resistor divider to give 1 v at the vs1 pin. t he vs1 trim register (register 0x38) is a djuste d until the vs1 value in register 0x15[15:4] reads 2560 decimal (0xa00). vs2 trim the vs2 input requires a gain trim. enable the power supply with no - load current. it is recommended that the vs2 voltage be div ided down by the vs2 resistor divider to give 1 v at the vs2 pin. the vs2 trim register (register 0x39) is adjusted until the vs2 value in register 0x16[15:4] reads 2560 decimal (0xa00). rtd/otp trim the rtd input requires two trims : one for the current so urce and one for the adc . t o use the internal linearization scheme, additional trimming procedures are required . trimming the current source bits[7:6] of register 0x11 set the value of the current source to 10 a, 20 a, 30 a, or 40 a. bits[5:0] of regi ster 0x11 can be used to fine - tune the current value. by fine - tuning the internal current source, component tolerance can be compensated for and errors can be minimized. one lsb in bits[5:0] = 160 na. a decimal value of 1 adds 160 na to the current source set by bits[7:6]; a decimal value of 63 adds 63 160 na = 10.08 a to the current source set by bits[7:6] . to program a value for the current source, select the nearest possible option (10 a, 20 a, 30 a, or 40 a) using register 0x11[7:6]. then use register 0x11[5:0] to achieve the finer step size. for example , to use a value of 46 a as the current source , follow these steps: 1. place a known resistor (rx) from rtd to agnd. 2. set register 0x11[7:6] to 11 ( 40 a ). 3. i ncrease the value of register 0x11[5:0] one lsb at a time until the voltage at the rtd pin is v rtd = 46 a rx. the current source is now calibrated and is set to the factory default value . trimming the adc due to the nonlinear nature of the thermistor , two trimming options can be us ed. using the internal linearization scheme the first option uses the internal linear ization scheme with 46 a rtd current , which provides an accurate reading in c read in r egister 0x1b in decimal format. a 100 k? , 1% ntc thermistor with beta = 4250, 1% (such as t he ncp15wf104f03rc) in parallel with an external resistor of 16.5 k?, 1% , should be used with the adp1046a . with this ntc thermistor and resistor combination, t he ad p1046a default current source trim is set to 46 a to achieve the best possible accuracy over temperatures ranging from 85c to 125 c. if an external microcontroller is used, the rtd adc code in register 0x1a can be fed into the microcontroller and a diff erent linearization scheme can be implemented in terms of a best - fit polynomial for the selected ntc characteristics . data sheet adp1046a rev. 0 | page 35 of 88 using the otp va lu e the second option does not use the linearization sche me. instead, the user program s an rtd current and set s the otp threshold in m illivolts . due to the nonlinear nature of the ntc thermistor , it is best to use a resistor in parallel with the ntc thermistor to aid in the linearization of the voltage seen at the rtd pin. this procedure trims out the errors/toleran ces in the ntc therm - istor and the external resistor. calculation of the parallel resistor can be done by knowing the ntc resistance characteristic across various temperatures. to use this procedure, the temperatures and equivalent resistances of the ntc t hermistor and parallel resistor combination must be known. i n figure 45 , t2 is the otp threshold that sets the otp flag, and t1 is the temperature at which the otp flag is cleared . rtd pin voltage v2 v1 adc code temperature rtd pin voltage v1 t1 t2 v2 1 1012-300 figure 45 . rtd pin v oltage, adc code, and temperature t he following procedure should be used: 1. adjust the desired rtd current source , i rtd , as described in the trimming the current source section. 2. set th e temperature to the otp threshold . 3. adjust the offset trim registers (register 0x1c and register 0x20 ) until the reading in register 0x1a is the same as v2 ( in mv). 4. s et the otp threshold ( register 0x2f) to the value of v2. 5. s et the temperature to the hysteresis point where the otp flag i s cleared. 6. a djust the temperature gain trim register (register 0x2b) until the correct voltage is seen in register 0x1a. t he adc is now trimmed and is linear between the two temperatures of interest. this procedure achieves the most accurate otp because it takes into account the part - to - part variations of the adp1046a and the tolerances of the thermistor being used. acsns calibration an d trim the acsns feedforward adc ( see figure 19 ) is used for voltage line feedforward and cannot be trimmed by the user. the acsns slow adc requires a gain trim. enable the power supply with full load current at the nominal input voltage. the secondary peak reverse voltage on the output rec tifiers is filtered by an external rcd circuit ( see figure 19) . to trim the acsns adc, the user can reverse - calculate the primary voltage as follows: v primary = vx ( r1 + r2 )/ r2 ( n1/ n2) where: vx is the voltage at the acsns pin . n1/ n2 is the turns ratio. the acsns gain trim register (register 0x5e) is adjusted until th is calculated voltage is equal to the desired primary input voltage. another way to trim the acsns adc uses the average second - ary voltage. with kn own values for the nominal input voltage, transformer turns ratio, and resistor dividers at the acsns pin, the acsns gain trim register (register 0x5e) is adjusted to give code 2560 decimal (0xa00). adc code = vx /1.6 4096 where vx is the voltage at the a csns pin . the resistors in figure 19 are sized such that the first time constant, rc, is long enough to prevent overcharging of the capacitor (roughly 200 ns in a typical application), whereas the second time const ant, ( r1 + r2) c, is long enough to keep the average voltage constant during the rectifier off time. adp1046a data sheet rev. 0 | page 36 of 88 layout guidelines this section explains best practices that should be followed to ensure optimal performance of the adp1046a . in general, place all components as close to the adp1046a as possible. all signals should be refer enc ed to their respective grounds. cs2+ and cs2? r out e the traces from the sense resistor to the adp1046a parallel to each other. keep t he traces close together and as far from the switch nodes as possible. vs3+ and vs3? route the traces from t he remote voltage sense point to the adp1046a parallel to each other. keep t he traces close together and as far from the switch nodes as possible. place a 100 nf capac - itor from vs3? to a g nd to reduce common - mo de noise. vdd place the decoupling capacitors as close to the part as possible. a 4.7 f capacitor from vdd to agnd is recommended. sda and scl route the traces to these pins parallel to each other. keep t he traces close together and as far from the switch nodes as possible. cs1 route the traces from the current sense transformer to the adp1046a parallel to each other. keep t he traces close together and as far from the switch nodes as possible. exposed pad sol der t he exposed pad underneath the adp1046a to the pcb agnd plane. vcore place a 330 nf decoupling capacitor from this pin to dgnd as close to the part as possible. res place a 10 k , 0.1% resistor from this p in to agnd as close to the part as possible. rtd route a single trace to the adp1046a from the thermistor using a dedicated trace to agnd. place the thermistor close to the hottest part of the power supply. agn d, dgnd, and pgnd create an agnd ground plane and make a single - point (star) connection to the power supply system ground. c onnect dgnd to agnd with a very short trace using a star connection. connect pgnd t o agnd using a star connection. data sheet adp1046a rev. 0 | page 37 of 88 i 2 c interface communication the adp1046a i 2 c slave is a 2 - wire interface that can be used to communicate with other i 2 c - compliant master devices and is compatible in a multimaster, multislave bus configuration. the functi on of the i 2 c slave is to decode the command sent from the master device and respond as requested. communication is established using a 2 - wire interface with a clock line (scl) and data line (sda). the i 2 c slave is designed to externally move chunks of 8 - b it data (bytes) while maintaining compliance with the i 2 c protocol, based on the philips i 2 c bus specification , v ersion 2.1, dated january 2000. the i 2 c protocol incorporates the following features: ? slave opera tion on multiple device systems ? 7 - bit addressi ng ? 100 kb/sec and 400 kb/sec data rates ? general call address support ? support for clock low extension (clock stretching) ? separate multiple byte receive and transmit fifo ? extensive communication fault monitoring i 2 c overview the i 2 c slave module is a 2 - wire interface that can be used to communicate with other i 2 c - compliant master devices. i ts transfer protocol is based on the i 2 c transfer mechanism. the adp1046a is always configured as a slave device in the overa ll system. the adp1046a communicates with the master device using one data pin (sda) and one clock pin (scl). because the adp1046a is a slave device, it cannot gene rate the clock signal . however, it is capable of stretching the scl line to p lace the master device in a wait state when it is not ready to respond to the masters request. communication is initiated when the master device send s a command to the i 2 c slave device. commands can be read or write com mands, in which case data is transferred between the devices in a byte - wide format. commands can also be send commands, in which case the command is executed by the slave device upon receiving the stop bit. the sto p bit is the last bit in a complete data transfer, as defined in the i 2 c communication protocol. during communication, the master and slave devices send acknowledge (a) or no acknowledge (na) bits as a method of handshaking between devices. refer to the p hilips i 2 c bus specification , v ersion 2.1, dated january 2000, for a more detailed description of the communication protocol. i 2 c address the i 2 c address of the adp1046a is set by connecting an external resis tor from the add pin to agnd. table 6 lists the recommended resistor values and the associated i 2 c addresses. seven different addresses can be used. the recommended resistor values in table 6 must be 1% tolerance resistors. table 6 . recommended resistor values for i 2 c addresses i 2 c address resistor value (k) 0x50 10 (or connect the add pin directly to agnd) 0x51 28.7 0x52 48.7 0x53 68.1 0x54 88.7 0x55 109 0x57 200 ( or connect the add pin directly to vdd ) data transfer format overview the i 2 c slave follows the transfer protocol of th e philips i 2 c bus specification . data transfers are byte - wi d e, lower byte first. each byte is transmitted serially, most significant bit (msb) first. a typical transfer is shown in figure 46. s 7-bit slave address w a a ... p 8-bit data = master-to-slave = slave-to-master 1 1012-140 figure 46 . basic data transfer figure 46 to figure 53 use the following abbreviations: ? s = start condition ? sr = repeated start condition ? p = stop condit ion ? r = read bit ? w = write bit ? a = acknowledg e bit (0) ? na = no acknowledge bit (1) refer to the i 2 c specification for an in - depth discussion of the transfer protocols. adp1046a data sheet rev. 0 | page 38 of 88 command overview data transfer using the i 2 c slave is established using commands. all commands start with a slave address with the r / w bit cleared (set to 0), followed by the command code (register address). all commands supported b y the adp1046a follow one of the protocol types shown in figure 47 to figure 53. s 7-bit slave address w a a p command code = master-to-slave = slave-to-master 1 1012-141 figure 47 . send byte protocol s 7-bit slave address w a a a p command code data byte = master-to-slave = slave-to-master 1 1012-142 figure 48 . write byte protocol s 7-bit slave address w a a data byte high command code data byte low a a p = master-to-slave = slave-to-master 1 1012-143 figure 49 . write word protocol data byte na p s 7-bit slave address w a a 7-bit slave address command code sr r a = master-to-slave = slave-to-master 1 1012-144 figure 50 . read byte protocol data byte low a na p data byte high s 7-bit slave address w a a 7-bit slave address command code sr r a = master-to-slave = slave-to-master 1 1012-145 figure 51 . read word protocol dat a byte 1 a ... a p dat a byte n s 7-bit sl a ve address w a a byte count = n command code a = master- t o-sl a ve = sl a ve- t o-master 1 1012-146 figure 52 . block write protocol s 7-bit sl a ve address 7-bit sl a ve address w a a command code a r sr dat a byte 1 a a ... na dat a byte n p byte count = n = master- t o-sl a ve = sl a ve- t o-master 1 1012-147 figure 53 . block read protocol clock generation and stretching the adp1046a is always a slave in the overall system ; therefore, the device never needs to generate the clock, which is done by the master device in the system. however, the i 2 c slave device is capable of clock st retching to p lace the master in a wait state. by stretching the scl signal during the low period, the slave device communicat es to the master device that it is not ready and that the master device must wait . conditions where the i 2 c slave device stretches the scl line low include the following: ? the master device is transmitting at a higher baud rate than the slave device. ? the receive fifo buffer of the slave device is full and must be read before continuing. this prevents a data overflow condition. ? the slav e device is not ready to send data that the master has requested. note that the slave device can stretch the scl line only during the low period. also, whereas the i 2 c specification allows indefinite stretching of the scl line, the adp1046a limits the maximum time that the scl line can be stretched, or held low. for more information about the maximum time , see t he timeout condition section. start and stop conditions star t and stop conditions involve serial data transitions while the serial clock is a t a logic hi gh level. the i 2 c slave device monitors the sda and scl lines to detect the start and stop conditions and transition its internal state machine accordingly. typica l start and stop conditions are show n in figure 54. scl sda st art st op 1 1012-148 figure 54 . start and stop transitions data sheet adp1046a rev. 0 | page 39 of 88 general call support the adp1046a is capable of decoding and ack nowledging a general call address. the general call address is supported for send, write, and read commands that use address 0x00 as the slave address. the i 2 c slave responds to both its own address and t o t he general call address (0x00). note that all com mands start with a slave address with the r/ w bit cleared (set to 0), followed by the command code. this is also true when using the general call address to communicate with the i 2 c slave device. 10- bit addressing the adp1046a does not support 10 - bit addressing as defined in the i 2 c specification. fast mode fast mode (400 kb/sec ) uses essentially the same mechanics a s the standard mode of operation; the electrical specifications and timing are most affected. the i 2 c slave is capable of commu - nicating with a master device operating in standard mode (100 kb/sec ) or fast mode. repeated start condi tion in general, a repeated start condition is the absence of a stop condition between two transfers. the two transfers can be of any direction type , for example, a transmit followed by a receive or a receive followed by a transmit . however, the adp1046a i 2 c communication protocol use s the repeated start condit ion only when performing a read access (read byte, read word, and block read). o ther uses of the repeated start condition are not allowed. electrical specifica tions all logic complies with the e lectrical s pecification s outlined in the philips i 2 c bus speci fication , v ersion 2.1, dated january 2000. fault conditions the i 2 c protocol provides a very comprehensive set of fault conditions that are monitored during communication. these communication faults are error conditions associated with the data transfer me chanism of the i 2 c protocol and are explained in the following sections . timeout condition a timeout condition occurs if any single scl clock pulse is held low for longer than the t timeout, min of 25 ms. upon detecting the timeout condition, the i 2 c slave device has 10 ms to abort the transfer, release the bus lines, and be ready to accept a new start condition. the device initiating the timeout is required to hold the scl clock line low for a minimum of t timeout, max = 35 ms, guaranteeing that the slave de vice is given enough time to reset its communication protocol. data transmission fa ults data transmission faults occur when two communicating devices violate the i 2 c communication protocol. sending too few bits transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been sent. not supported; any transmitted data is ignored. reading too few bits transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been read. not suppor ted; any received data is ignored. host sends or reads too few bytes if a host ends a packet with a stop condition before the required bytes are sent/received, it is assumed th at th e host intended to stop the transfer . therefore, the i 2 c slave does not con sider this to be an error and t akes no action, except to flush any remain - ing bytes in the transmit fifo. host sends too many bytes if a host sends more bytes than are expected for the corre - sponding command, the i 2 c slave considers this a data transmissio n fault and responds as follows: ? issues a no acknowledge for all unexpected bytes as they are received ? flushes and ignores the received command and data host reads too many bytes if a host reads more bytes than are expected for the corre - sponding command, the i 2 c slave considers this a data transmission fault and se nd s all 1s (0xff) as long as the host continue s to request data . device busy the i 2 c slave device is too busy to respond to a request from the master device. typically scl clock stretching is inv olved until the device is free to communicate. data content faults data content faults occur when data transmission is successful, but the i 2 c s lave device cannot process the data that is received from the master device. improperly set read bit in the addr ess byte all i 2 c commands start with a slave address with the r/ w bit cleared (set to 0), followed by the command code. if a host starts an i 2 c transaction with r/ w set in the address phase (equivalent to an i 2 c read), t he i 2 c slave considers this a data content fault and responds as follows: ? acknowledges the address byte ? issues a no acknowledge for the command and data bytes ? sends all 1s (0xff) as long as the host continues to request data adp1046a data sheet rev. 0 | page 40 of 88 invalid or unsupported command code if an invalid or unsupported command code is sent to the i 2 c slave, the i 2 c slave considers this a data content fault and responds as follows: ? issues a no acknowledge for the illegal/unsupported command byte and data bytes ? flushes and ignores the r eceived command and data reserved bits accesses to reserved bits are not a fault. writes to reserved bits are ignored, and reads from reserved bits return undefined data. write to read - only commands if a host performs a write to a read - only command, the i 2 c slave considers this a data content fault and responds as follows: ? issues a no acknowledge for all unexpected data bytes as they are received ? flushes and ignores the received command and data note that this is the same error described in the host sends too many bytes section. read from write - only commands if a host performs a read from a write - only command, the i 2 c slave considers this a data content fault and s end all 1s (0xff) as long as the host continue s to request data . n ote that this is the same error described in the host reads too many bytes section. data sheet adp1046a rev. 0 | page 41 of 88 eeprom the adp1046a has a built - in eeprom c ontroller that is used to communicate with the embedd ed 8k 8 - byte eeprom. the eeprom, also called flash?/ee, is partitioned into two major blocks: the info block and the main block . the info block contains 128 8 - bit bytes (for internal use only ), and the main block contains 8k 8 - bit bytes. the main block i s further parti - tioned into 16 pages, each page containing 512 bytes. eeprom overview the eeprom controller provides an interface between the adp1046a core logic and the built - in flash/ee. the user can control data access to and from the eeprom through this controller interface. different i 2 c commands are available for the different operations to the eeprom. communication is initiated by the master device sending a command to the i 2 c slave device to access data from or send data to the eeprom. using read and write commands , data is transferred between devices in a byte - wide format. using a read command, data is received from the eeprom and transmitted to the master device. using a write command, data is received from the master device and stored in the eeprom through the eeprom controller. s end commands are also supported , in which case the command is executed by the slave device upon receiving the stop bit. the stop bit is the last bit in a complete data transfer , as defined in the i 2 c communication protocol. for a complete description of the i 2 c protocol, see the philips i 2 c bus specification , v ersion 2.1, dated january 2000. page erase operation the main block consists of 16 equivalent pages of 512 bytes each, numbered page 0 to page 15. page 0 and page 1 of the main block are reserved for storing the default settings and user settings, respectively. the user cannot perform a page erase operation on page 0 or page 1. page 2 and page 3 are reserved for internal use ; do not erase t he contents of page 2 or page 3 . only page 4 to page 15 of the main block should be used to store data. to erase any page from page 4 to page 15, the eeprom must first be unlocked for access. for instructions on how to unlock the eeprom, see the unlock the eeprom section. page 4 to page 15 of the main block can be individually erased using the eeprom_page_erase command (register 0x87). for example, to perform a page erase of page 10, execute the following command : s 7-bit slave address w a a p data byte command code a = master-to-slave = slave-to-master 1 1012-200 figure 55 . example erase command in this example, c ommand c ode = 0x 87 and d ata b yte = 0x0a. note that it is necessary to wait at least 35 ms for the page erase operation to complete before executing the next i 2 c command. the ee prom allows erasing of whole pages only; therefore, to change the data of any single byte in a page, the entire page must first be erased (set high) for that byte to be writable. subsequent writes to any bytes in that page are allowed as long as that byte has not been written to a logic low previously. read operation (byte read and block read) read from main block, page 0 and page 1 page 0 and page 1 of the main block are reserved for storing the default settings and user settings, respectively, and are in tended to prevent third - party access to this data. to read from page 0 or page 1, the user must first unlock the eeprom (see the unlock the eeprom section). after the eeprom is unlocked, page 0 and page 1 are reada ble using the eeprom_data_xx commands, as described in the read from main block, page 2 to page 15 section. note that when the eeprom is locked, a read from page 0 or page 1 returns invalid data. read from main blo ck, page 2 to page 15 data in page 2 to page 15 of the main block is always readable, even with the eeprom locked. the data in the eeprom main block can be read one byte at a time or in multiple bytes in series using the eeprom_data_xx commands ( register 0 x 8b to register 0x 9a ). before executing this command, the user must program the number of bytes to read using the eeprom_num_rd_bytes command (register 0x86 ). the user can also program the offset from the page boundary where the first read byte is returned using the eeprom_addr_offset command ( register 0x85 ). in the following example, three bytes from page 4 are read from the eeprom, starting from the fifth byte of that page. 1. set the number of return bytes = 3. s 7-bit slave address w a a p 0x86 0x03 a = master-to-slave = slave-to-master 1 1012-201 2. set address offset = 5. s 7-bit slave address w a a a a p 0x85 0x05 0x00 = master-to-slave = slave-to-master 1 1012-202 3. read three bytes f rom page 4 . s 7-bit slave address 7-bit slave address w a a r a 0x8f sr byte count = 0x03 data byte 3 a a na p data byte 1 ... = master-to-slave = slave-to-master 1 1012-203 note that the block read command can read a maximum of 256 bytes for a ny single transaction (set the number of return bytes = 0). adp1046a data sheet rev. 0 | page 42 of 88 write operation (byt e write and block write) write to main block, page 0 and page 1 page 0 and page 1 of the ma in block are reserved for storing the default settings and user settings, respectively. the user cannot perform a direct write operation to page 0 or page 1 using the eeprom_data_ 00 and eeprom_data_ 01 commands. a user write to page 0 or page 1 returns a no acknowledge. to program the register contents of page 1 of the main block, it is recommended that the store_user_all command be used ( register 0x82 ). see the save register settings to user settings section. write to main block, page 2 and page 3 page 2 and page 3 of the main block are reserved for internal use and their contents should not be written to. only page 4 to page 15 should be used to store data. write to main block, page 4 to page 15 before performing a write to page 4 through page 15 of the main block, the user must first unlock the eeprom (see the unlock the eeprom section). data in page 4 to page 15 of the eeprom main block can be programmed (written to) one byte at a time or in multiple bytes in series using the eeprom_data_xx commands (register 0x8b to register 0x9a). before executing this command, the user can program the offset from the page boundary where the first byte is written using the eeprom_addr_offset command (reg ister 0x85). if the targeted page has not yet been erased, the user can erase the page as described in the page erase operation section. in the following example, four bytes are written to page 9, starting from the 256 th byte of t hat page. 1. set address offset = 256. s 7-bit sl a ve address w a a 0x01 a a p 0x85 0x00 = master- t o-sl a ve = sl a ve- t o-master 1 1012-204 2. write four bytes to page 9. s 7-bit slave address byte count = 4 w a a a 0x94 data byte 1 data byte 4 a a p ... = master-to-slave = slave-to-master 1 1012-205 note that the block write command can write a maximum of 256 bytes for any single transaction (set the byte count = 0). eeprom password on power - up, the eeprom is locked and protected f rom accidental writes or erases. only reads from page 2 to page 15 of the main block are allowed when the eeprom is locked. before any data can be written (programmed) to the eeprom, the eeprom must be unlocked for write access. after it is unlocked, the eeprom is opened for reading, writing, and erasing. unlock the eeprom to unlock the eeprom, perform two consecutive writes with the correct password (default = 0xff) using the eeprom_ password command ( register 0x88 ). the eeprom unlocked flag (bit 0 of re gister 0x 03 ) is set to indicate that the eeprom is unlocked for write access. lock the eeprom to lock the eeprom, write any byte other than the correct pass - word using the eeprom_password command (register 0x88). the eeprom unlocked flag (bit 0 of register 0x03) is cleared to indicate that the eeprom is locked from write access. change the eeprom password to change the eeprom password, first write the correct password using the eeprom_password command (register 0x88). immediately write the new password usin g the same command. the password is now changed to the new password. downloading eeprom settings to internal registers download user settings to registers the user settings are stored in page 1 of the eeprom main block. these settings are downloaded from t he eeprom into the registers under the following conditions: ? on power - up . t he user settings are automatically down - loaded into the internal registers, powering the part up in a state previously saved by the user. ? on execution of the restore_user_all comma nd (register 0x83). this command allows the user to force a download of the user settings from page 1 of the eeprom main block into the internal registers. download factory default settings to registers the factory default settings are stored in page 0 of the eeprom main block. the factory default settings can be downloaded from the eeprom into the internal registers using the restore_ default_all command ( register 0x81 ). when this command is executed, the eeprom password is also reset to the factory defaul t setting of 0xff. data sheet adp1046a rev. 0 | page 43 of 88 saving register settings to the eeprom the register settings cannot be saved to the factory default set - tings located in page 0 of the eeprom main block. this is to prevent the user from accidentally overriding the factory trim settin gs and default register settings. save register settings to user settings the register settings can be saved to the user settings located in page 1 of the eeprom main block using the store_user_all command (register 0x82). before this command can be execut ed, the eeprom must first be unlocked for writing (see the unlock the eeprom section). after the register settings are saved to the user settings, any subsequent power cycle automatically downloads the latest store d user information from the eeprom into the internal registers. note that execution of the store_user_all command auto - matically performs a page erase to page 1 of the eeprom main block, after which the register settings are stored in the eeprom. therefore , it is important to wait at least 40 ms for the operation to complete before executing the next i 2 c command. eeprom crc checksum as a simple method of checking that the values downloaded from the eeprom are consistent with the internal registers, a crc checksum is implemented. ? when the data from the internal registers is saved to the eeprom (page 1 of the main block), the total number of 1s from all the registers is counted and written into the eeprom as the last byte of information. this is called the crc checksum. ? when the data is downloaded from the eeprom into the internal registers, a similar counter that sums all 1s from the values loaded into the registers is saved. this value is compared with the crc checksum from the previous upload operati on. if the values match, the download operation was successful. if the values differ, the eeprom download operation failed, and the eeprom crc fault flag is set (bit 1 of register 0x 03). to read the eeprom crc checksum value, execute the eeprom _ crc_chksum command ( register 0x84 ). this command returns the crc checksum accumulated in the counter during the download operation. note that the crc checksum is an 8 - bit cyclical accumulator that wraps around to 0 when 255 is reached. adp1046a data sheet rev. 0 | page 44 of 88 software gui a free soft ware gui is available for programming and configu - ring the adp1046a . the gui is designed to be intuitive to power supply designers and dramatically reduces power supply design and development time. the software includes filter design and power supply pwm topology windows. the gui is also an information center, displaying the status of all readings, monitoring, and flags on the adp1046a . for more information about t he gui, contact analog devices for the latest software and a user guide. evaluation boards are also available by contacting analog devices. 1 1012-407 figure 56 . adp1046a gui data sheet adp1046a rev. 0 | page 45 of 88 register lis ting table 7 . register list address register name fault registers 0x00 fault register 1 0x01 fault register 2 0x02 fault register 3 0x03 fault register 4 0x04 latched fault register 1 0x05 latched fault register 2 0x06 latch ed fault register 3 0x07 latched fault register 4 0x08 fault configuration register 1 0x09 fault configuration register 2 0x0a fault configuration register 3 0x0b fault configuration register 4 0x0c fault configuration register 5 0x0d fault configur ation register 6 0x0e flag configuration 0x0f soft start blank fault flags value registers 0x10 first flag id 0x11 rtd current source 0x12 hf adc reading 0x13 cs1 value (input current) 0x14 acsns value 0x15 vs1 voltage value 0x16 vs2 voltage valu e 0x17 vs3 voltage value (output voltage) 0x18 cs2 value (output current) 0x19 cs2 vs3 value (output power) 0x1a rtd temperature value 0x1b read temperature 0x1c rtd offset trim ( msb ) 0x1d share bus value 0x1e modulation value 0x1f line impedanc e value 0x20 rtd offset trim (lsbs) current sense and current limit registers 0x21 cs1 gain trim 0x22 cs1 accurate ocp limit 0x23 cs2 gain trim 0x24 cs2 analog offset trim 0x25 cs2 digital offset trim 0x26 cs2 accurate ocp limit 0x27 cs1/cs2 fast ocp settings 0x28 volt - second balance settings 0x29 share bus bandwidth 0x2a share bus setting 0x2b temperature gain trim 0x2c pson/soft start 0x2d pgood debounce and pin polarity setting s 0x2e modulation limit 0x2f otp threshold 0x30 orfet adp1046a data sheet rev. 0 | page 46 of 88 address register name volta ge sense registers 0x31 vs3 voltage setting (remote voltage) 0x32 vs1 overvoltage limit (ovp) 0x33 vs2 and vs3 overvoltage limit (ovp) 0x34 vs1 undervoltage limit (uvp) 0x35 line impedance limit 0x36 load line impedance 0x37 fast ovp comparator 0x3 8 vs1 trim 0x39 vs2 trim 0x3a vs3 trim 0x3b light load mode disable setting s id registers 0x3c silicon revision id 0x3d manufacturer id 0x3e device id pwm and synchronous rectification timing registers 0x3f outaux switching frequency setting 0x40 pwm switching frequency setting 0x41 outa rising edge timing (outa pin) 0x42 outa rising edge setting (outa pin) 0x43 outa falling edge timing (outa pin) 0x44 outa falling edge setting (outa pin) 0x45 outb rising edge timing (outb pin) 0x46 outb ris ing edge setting (outb pin) 0x47 outb falling edge timing (outb pin) 0x48 outb falling edge setting (outb pin) 0x49 outc rising edge timing (outc pin) 0x4a outc rising edge setting (outc pin) 0x4b outc falling edge timing (outc pin) 0x4c outc falling edge setting (outc pin) 0x4d outd rising edge timing (outd pin) 0x4e outd rising edge setting (outd pin) 0x4f outd falling edge timing (outd pin) 0x50 outd falling edge setting (outd pin) 0x51 sr1 rising edge timing (sr1 pin) 0x52 sr1 rising edge se tting (sr1 pin) 0x53 sr1 falling edge timing (sr1 pin) 0x54 sr1 falling edge setting (sr1 pin) 0x55 sr2 rising edge timing (sr2 pin) 0x56 sr2 rising edge setting (sr2 pin) 0x57 sr2 falling edge timing (sr2 pin) 0x58 sr2 falling edge setting (sr2 pin) 0x59 outaux rising edge timing (outaux pin) 0x5a outaux rising edge setting (outaux pin) 0x5b outaux falling edge timing (outaux pin) 0x5c outaux falling edge setting (outaux pin) 0x5d outx and srx pin disable setting s 0x5e acsns gain trim digital filter programming registers 0x5f soft start and output voltage slew rate settings 0x60 normal mode digital filter lf gain setting 0x61 normal mode digital filter z ero setting 0x62 normal mode digital filter pole setting 0x63 normal mode digital filte r hf gain setting 0x64 light load mode digital filter lf gain setting data sheet adp1046a rev. 0 | page 47 of 88 address register name 0x65 light load mode digital filter z ero setting 0x66 light load mode digital filter pole setting 0x67 light load mode digital filter hf gain setting 0x68 reserved soft start filte r programming registers 0x71 soft start digital filter lf gain setting 0x72 soft start digital filter z ero setting 0x73 soft start digital filter pole setting 0x74 soft start digital filter hf gain setting extended functions registers 0x75 voltage li ne feedforward 0x76 volt - second balance settings (outa and outb pins) 0x77 volt - second balance settings (outc and outd pins) 0x78 volt - second balance settings (sr1 and sr2 pins) 0x79 sr delay compensation 0x7a filter transitions 0x7b pgood1 flag mask ing 0x7c pgood2 flag masking 0x7d light load mode threshold settings 0x7e reserved 0x7f go byte 0x80 reserved eeprom registers 0x81 restore_default_all 0x82 store_user_all 0x83 restore_user_all 0x84 eeprom_crc_chksum 0x85 eeprom_addr_offset 0x8 6 eeprom_num_rd_bytes 0x87 eeprom_page_erase 0x88 eeprom_password 0x89 trim_password 0x8a eeprom_info 0x8b eeprom_data_00 0x8c eeprom_data_01 0x8d eeprom_data_02 0x8e eeprom_data_03 0x8f eeprom_data_04 0x90 eeprom_data_05 0x91 eeprom_data_06 0x 92 eeprom_data_07 0x93 eeprom_data_08 0x94 eeprom_data_09 0x95 eeprom_data_10 0x96 eeprom_data_11 0x97 eeprom_data_12 0x98 eeprom_data_13 0x99 eeprom_data_14 0x9a eeprom_data_15 adp1046a data sheet rev. 0 | page 48 of 88 detailed register de scriptions fault registers register 0x04 to regis ter 0x07 are latched fault registers. in these registers, flags are not reset when the fault disappears. flags are cleared only by a register read (provided that the fault no longer persists). note that latched bits are clocked on a low - to - high transition only. also note that these register bits are cleared when read via the i 2 c interface unless the fault is still present. it is recommended that the latched fault register be read again after the faults disappear to ensure that the register is reset. table 8 . register 0x00 fault register 1 and register 0x04 latched fault register 1 (1 = fault, 0 = normal operation) bits bit name r/w description register action 7 power supply r 1 = power supply is off. all pwm outputs are disabled. thi s bit stays high until the power supply is restarted. none 6 orfet r 1 = orfet control signal at the gate pin (pin 16) is off. 0x30 5 pgood1 fault r 1 = power - good 1 fault. at least one of the following flags has been set: soft start flag, cs1 fast ocp , cs1 accurate ocp, cs2 accurate ocp, uvp, local ovp, load ovp, or orfet (gate pin ). these flags can be masked using register 0x7b . 0x2d none 4 pgood2 fault r 1 = power - good 2 fault. at least one of the following flags has been set: s oft start flag, cs1 f ast ocp, cs1 accurate ocp, cs2 accurate ocp, uvp, local ovp, load ovp, or orfet (gate pin ). these flags can be masked using register 0x7c . the following flag s can also set pgood2, either unconditionally or based on the flag response, as defined in register 0x2d[3] ( see table 45) : voltage continuity, orfet disable, acsns, external flag (flagin pin ), and o t p. 0x2d none 3 sr off r sr1 and sr2 synchronous rectifiers are disabled. this flag is set when one of the follow ing cases is true: none sr1 and sr2 are disabled by the user. 0x5d the load current has fallen below the threshold in register 0x3b. 0x3b a flag has been set that is configured to disable the synchronous rectifiers. 0x08 to 0x0d 2 cs1 fas t ocp r cs1 current is above its fast overcurrent protection limit. there is a 1.2 v threshold on the cs1 pin. fast ocp is a comparator. programmable 1 cs1 accurate ocp r cs1 current is above its accurate overcurrent protection limit. 0x22 programmable 0 cs2 accurate ocp r cs2 current is above its accurate overcurrent protection limit. 0x26 programmable table 9 . register 0x01 fault register 2 and register 0x05 latched fault register 2 (1 = fault, 0 = normal operation) bits bit n ame r/w description register action 7 voltage continuity r voltage differential between vs1 and vs2 pins or between vs2 and vs3 pins is outside limits. either (vs1 ? vs2) > 50 mv or (vs2 ? vs3) > 50 mv at the pins. programmable 6 uvp r vs1 is below its undervoltage limit. 0x34 programmable 5 cs2 reverse curre nt r reverse voltage across the cs2 pins is above limit. this is the orfet reverse voltage. 0x30 programmable 4 vdd uv r vdd is below limit. immediate shutdown 3 vcore ov r 2.5 v vcore is above limit. immediate shutdown 2 vdd ov r vdd is above limit. the i 2 c interface stays functional, but a pson toggle is required to restart the power supply. 0x0e programmable 1 load ovp r vs2 or vs3 is above its overvoltage limit. 0x33 programmable 0 local ovp r vs1 is above its overvoltage limit. 0x32 programmab le data sheet adp1046a rev. 0 | page 49 of 88 table 10 . register 0x02 fault register 3 and register 0x06 latched fault register 3 (1 = fault, 0 = normal operation) bits bit name r/w description register action 7 otp r temperature is above otp limit . 0x2f programmable 6 fast ovp r fast ovp threshold was exceeded. 0x37 programmable 5 share bus r current share is outside regulation limit . 0x2a programmable 4 constant current r power supply is operating in constant current mode (constant current mode is enabled) . 0x27 none 3 soft start r the reference is being ramped . none 2 line impedance r line impedance between vs2 and vs3 is above limit . 0x35 none 1 soft start filter r the soft start filter is in use . 0x5f none 0 external flag r the external flag pin (flagin) is s et . programmable table 11 . register 0x03 fault register 4 and register 0x07 latched fault register 4 (1 = fault, 0 = normal operation) bits bit name r/w description register action 7 volt - sec ond balance r volt - second balance is at its maximum or minimum limit . none 6 modulation r modulation is at its maximum or minimum limit . 0x2e none 5 reserved r reserved . none 4 light load mode r the system is in light load mode . 0x3b none 3 reserved r reserved. none 2 acsns r the ac s ense (comparator) amplitude is not correct . programmable 1 crc fault r the eeprom contents downloaded are incorrect . immediate shutdown 0 eeprom unlocked r the eeprom is unlocked . none table 12 . register 0x08 to register 0x0d fault configuration registers register name address bits flag shutdown debounce fault configuration register 1 0x08 [7:4] cs1 fast ocp see register 0x27 in table 39 [3:0] cs1 accurate ocp see register 0x0e in table 14 fault configuration register 2 0x09 [ 7 : 4 ] cs2 accurate ocp see register 0x0e in table 14 [3:0] load ovp (vs2 or vs3) 2 ms fault configuration register 3 0x0a [7:4] local a ccurate ovp (vs1) and f ast ovp (vs1 ) 2 ms ( s ee register 0x37 in table 55) [3:0] external flag input (flagin) 10 ms fault configuration register 4 0x0b [7:4] otp 100 ms [3:0] uvp 10 ms fault configuration register 5 0x0c [7:4] cs2 reverse vo ltage 10 ms [3:0] voltage continuity 100 ms fault configuration register 6 0x0d [7:4] share bus 100 ms [3:0] acsns 10 ms adp1046a data sheet rev. 0 | page 50 of 88 register 0x08 to register 0x0d allow the user to program the response when each flag is set. table 13 . register 0x08 to register 0x0d fault configuration register bit descriptions bits bit name r/w description 7 timing r/w this bit specifies when the flag is set. 0 = after debounce. 1 = immediately. [6:4] action r/w these bits specify the action that th e part takes in response to the flag. bit 6 bit 5 bit 4 action 0 0 0 ignore flag completely 0 0 1 disable sr1 and sr2 0 1 0 disable orfet 0 1 1 disable the power supply and reenable it after the power supply reenable time set in registe r 0x0e[ 1:0] 1 0 0 disable outaux 1 0 1 disable all pwm output s except outaux 1 1 0 disable sr1, sr2 , and orfet 1 1 1 disable the power supply and keep it disabled; pson signal is necessary to restart 3 timing r/w same as bit 7 . [2:0] acti on r/w same as bits[6:4]. table 14 . register 0x0e flag configuration register bits bit name r/w description 7 vdd ov/vcore ov flags ignore r/w setting this bit to 1 means that the vdd ov and vcore ov flags are ignored. 6 vdd ov/ vcore ov restart r/w this bit specifies whether the part downloads the eeprom contents before it restarts. 1 = if the part shuts down, it downloads the eeprom contents again before restarting. 0 = if the part shuts down, it does not download the eeprom co ntents again before restarting. 5 vdd ov/vcore ov debounce r/w setting this bit to 1 means that there is a 500 s debounce before the part shuts down. setting this bit to 0 means that there is a 2 s debounce before the part shuts down. [4:2] accurate ocp debounce for cs1 and cs2 r/w when an accurate ocp flag is set, there is a debounce time before the flag action is performed. these bits set the flag debounce time . the adc sampling rate ad ds a variable latency from 2.62 ms to 5.24 ms to this debounce time. bit 4 bit 3 bit 2 debounce 0 0 0 2.6 ms 0 0 1 9.8 ms 0 1 0 130 ms 0 1 1 260 ms 1 0 0 600 ms 1 0 1 1.3 sec 1 1 0 2 sec 1 1 1 2.6 sec [1:0] power supply re enable time r/w these bits specify the time delay before restarting the power supply after a shutdown. sr1, sr2, and orfet are reenabled immediately. bit 1 bit 0 time (sec) 0 0 0.5 0 1 1 1 0 2 1 1 4 data sheet adp1046a rev. 0 | page 51 of 88 register 0x0f allow s the user to program the adp1046a to ignore the specified flags until the end of the soft st art ramp time. the uvp and acsns flags are always active during soft start. table 15 . register 0x0f soft start blank fault flags register bits bit name r/w description 7 blank sr r/w setting this bit means that the sr1 and sr2 pwm outputs are not enabled until the end of the soft start ramp time. 6 blank otp r/w setting this bit means that the otp flag is ignored until the end of the soft start ramp time. 5 blank flagin r/w setting this bit means that the flagin flag is ignored un til the end of the soft start ramp time. 4 blank local ovp (accurate and fast) r/w setting this bit means that the local ovp flag is ignored until the end of the soft start ramp time. 3 blank load ovp r/w setting this bit means that the load ovp flag is ignored until the end of the soft start ramp time. 2 blank cs2 accurate ocp r/w setting this bit means that the cs2 accurate ocp flag is ignored until the end of the soft start ramp time. 1 blank cs1 accurate ocp r/w setting this bit means that the cs1 accurate ocp flag is ignored until the end of the soft start ramp time. 0 blank cs1 fast ocp r/w setting this bit means that the cs1 fast ocp flag is ignored until the end of the soft start ramp time. value registers table 16. r egister 0x10 first flag id bits bit name r/w description [7:4] reserved r reserved. [3:0] first flag id r these bits record the flag that was set first. restarting the power supply resets this register. reading this register also resets the register. bit 3 bit 2 bit 1 bit 0 fault register flag 0 0 0 0 none no flag 0 0 0 1 register 0x01, bit 3 vcore ov 0 0 1 0 register 0x01, bit 2 vdd ov 0 0 1 1 register 0x03, bit 1 eeprom crc fault 0 1 0 0 register 0x00, bit 2 cs1 fast ocp 0 1 0 1 register 0x00, bit 1 cs1 accurate ocp 0 1 1 0 register 0x00, bit 0 cs2 accurate ocp 0 1 1 1 register 0x01, bit 1 load ovp 1 0 0 0 register 0x01, bit 0 local ovp (fast and accurate) 1 0 0 1 register 0x02, bit 0 flagin 1 0 1 0 registe r 0x02, bit 7 otp 1 0 1 1 register 0x01, bit 6 uvp 1 1 0 0 register 0x01, bit 5 cs2 reverse current 1 1 0 1 register 0x01, bit 7 voltage continuity 1 1 1 0 register 0x02, bit 5 share bus 1 1 1 1 register 0x03, bit 2 acsns table 17 . register 0x11 rtd current source bits bit name r/w description [7:6] rtd c urrent s etting r/w these bits set the size of the current source on the rtd pin. bit 7 bit 6 current source (a) 0 0 10 0 1 20 1 0 30 1 1 4 0 [5:0] current t rim r/w these six bits are used to trim the current source on the rtd pin. each lsb corresponds to 160 n a , independent of the rtd current setting selected in r eg ister 0x11[7:6] . adp1046a data sheet rev. 0 | page 52 of 88 table 18 . register 0x12 hf adc rea ding bits bit name r/w description [7:0] hf adc reading r this register contains the reading from the high frequency adc. table 19 . register 0x13 cs1 value (input current) bits bit name r/w description [15:4] input current value r this register contains the 12 - bit input current information. this value is derived from a voltage measurement at the cs1 input. to read the input current information, this register must be read using two consecutive read operations. the eight bits of th e first read return the eight msbs of the input current information. the top four bits of the second read return the four lsbs of the input current information. the range of the cs1 input pin is from 0 v to 1.4 v . this value has 12 bits of resolution, whic h results in an lsb size of 342 v. at 0 v input, the value in this register is 0 (0x000). at 1 v input, the value in this register is 2926 (0xb6e). [3:0] reserved r reserved. table 20 . register 0x14 acsns value bits bit name r/w description [15:4] acsns voltage value r this register contains the 12 - bit acsns slow adc voltage information. [3:0] reserved r reserved. table 21 . register 0x15 vs1 voltage value bits bit name r/w description [15:4] vs1 volt age value r this register contains the 12 - bit local output voltage information. this voltage is measured at the vs1 pin. to read the vs1 voltage information, this register must be read using two consecutive read operations. the eight bits of the first rea d return the eight msbs of the local output voltage information. the top four bits of the second read return the four lsbs of the local output voltage information. the range of the vs1 input pin is from 0 v to 1.6 v . this value has 12 bits of resolution, w hich results in an lsb size of 390.625 v. at 0 v input, the value in this register is 0 (0x000). the recommended nominal voltage at this pin is 1 v. at 1 v input, these bits read 2560 (0xa00). [3:0] reserved r reserved. table 22 . register 0x16 vs2 voltage value bits bit name r/w description [15:4] vs2 voltage value r this register contains the 12 - bit load output voltage information. this voltage is measured at the vs2 pin. to read the load vs2 voltage information, this register must be read using two consecutive read operations. the eight bits of the first read return the eight msbs of the load output voltage information. the top four bits of the second read return the four lsbs of the load output voltage information. the range o f the vs2 input pin is from 0 v to 1.6 v . this value has 12 bits of resolution, which results in an lsb size of 390.625 v. at 0 v input, the value in this register is 0 (0x000). the recommended nominal voltage at this pin is 1 v. at 1 v input, these bits read 2560 (0xa00). [3:0] reserved r reserved. table 23 . register 0x17 vs3 voltage value (output voltage) bits bit name r/w description [15:4] vs3 voltage value r this register contains the 12 - bit remote output voltage informatio n. this value is the differential voltage between the vs3+ and vs3? pins. to read the remote output voltage information, this register must be read using two consecutive read operations. the eight bits of the first read return the eight msbs of the remote output voltage information. the top four bits of the second read return the four lsbs of the remote output voltage information. the range of the vs3 input pin s is from 0 v to 1.6 v . this value has 12 bits of resolution, which results in an lsb size of 390 .625 v. at 0 v input, the value in this register is 0 (0x000). the recommended nominal voltage at this pin is 1 v. at 1 v input, these bits read 2560 (0xa00). [3:0] reserved r reserved. data sheet adp1046a rev. 0 | page 53 of 88 table 24 . register 0x18 cs2 value (output current) bits bit name r/w description [15:4] output current value r this register contains the 12 - bit output current information. this value is the voltage drop across the sense resistor. t o obtain the current value , t he user must divide th e value of th is register by the sense resistor value (see the cs2+, cs2 ? pins section) . the cs2 pin s ha ve a full - scale input range of 120 mv or 60 mv (set in register 0x27[5]) . this value has 12 bits of resolution ; the lsb step size de pends on the input range value. when the cs2 input range is set to 120 mv , the lsb step si ze is 29.30 v. for example, at a 30 mv input signal on cs2, t he value in this register is 30 mv/29.30 v = 1024 (0x400). when the cs2 input range is set to 60 mv, the lsb step size is 14.65 v. for example, at a 30 mv input signal on cs2, th e value in this register is 30 mv/ 14.65 v = 2048 (0x800). [3:0] reserved r reserved. table 25 . register 0x19 cs2 vs3 value (output power) bits bit name r/w description [15:0] output power value r this register contains the 16 - bit output power information. this value is the product of the remote output voltage value (vs3) and the output current reading (cs2). see the power readings section for the formulas needed to convert this digital reading in to power information. table 26 . register 0x1a rtd temperature value bits bit name r/w description [15:4] temperature value r this register contains the 12 - bit output temperature information, as determined from the rtd pin. the ra nge of the rtd pin is from 0 v to 1.6 v . this value has 12 bits of resolution, which results in an lsb size of 390.625 v. at 0 v input, the value in this register is 0 (0x000). the recommended nominal voltage at this pin is 1 v. at 1 v input, these bits r ead 2560 (0xa00). [3:0] reserved r reserved. table 27 . register 0x1b read temperature bits bit name r/w description [7:0] read temperature r/w this register returns an 8 - bit temperature in c ( unsigned decima l format) . f or this feature to function correctly , the exter nal thermistor must be 100 k? with a 16.5 k?, 1% resistor in paralle l, and th e selected current source must be trimmed to 46 a by selecting 40 a in regist er 0x11[7:6] and using the current trim ( fine - trim ) bits in register 0x11[5:0]. table 28 . register 0x1c rtd offset trim ( msb ) bits bit name r/w description [7:2] reserved r reserved. 1 trim p olarity r/w setting this bit to 1 means that negative offset is introduced. setting this bit to 0 means that positive offset is introduc ed. 0 rtd o ffset t rim (msb) r/w this bit i s the msb of the rtd offset trim. t ogether with register 0x 20 (the lsbs ) , this bit set s the amount of offset trim that is applied to the rtd adc reading . table 29 . register 0x1d share bus value bits bit name r/w description [7:0] share bus value r this register contains the 8 - bit share bus voltage information. if the power supply is the master, this register outputs 0. table 30 . register 0x1e modulation value bit s bit name r/w description [7:0] modulation value r this register contains the 8 - bit modulation information. it outputs the amount of modulation from 0% to 100% that is being placed on the modulating edges. table 31 . register 0x 1f line impedance value bits bit name r/w description [7:0] line impedance value r this register contains the 8 - bit line impedance information. this value is (vs2 ? vs3)/cs2. table 32 . register 0x20 rtd offset trim (lsb s ) bits bi t name r/w description [7:0] rtd offset trim (lsbs) r/w these eight bits, together with register 0x1c[0] (the msb ) , set the amount of offset trim that is applied to the rtd adc reading . adp1046a data sheet rev. 0 | page 54 of 88 current sense and current limit registers table 33. register 0x21cs1 gain trim bits bit name r/w description 7 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] cs1 gain trim r/w this value calibrates the primary side current sense gain. see the cs1 trim section for more information. table 34. register 0x22cs1 accurate ocp limit bits bit name r/w description [7:5] cs1 fast ocp blanking r/w these bits determine the blanking time for cs1 before fast ocp is enabled. this time is measured from the start of a switching cycle. if using outaux, the time is synchronized with the rising edge of outaux. bit 7 bit 6 bit 5 delay (ns) 0 0 0 0 0 0 1 40 0 1 0 80 0 1 1 120 1 0 0 200 1 0 1 400 1 1 0 600 1 1 1 800 [4:0] cs1 accurate ocp r/w these bits set the cs1 accurate ocp threshold. th e digital word that is output from the cs1 adc is compared with this threshold. if the cs1 ad c reading (register 0x13) is greater than the ocp threshold set by these bits, the cs1 accurate ocp flag is set. this value should be programmed only after the cs1 trim has been performed. the range of these bits is from 0 to 31, that is, 0 v to 1.4 v in 43.75 mv steps. the following equation gives the cs1 accurate ocp threshold: cs1_ocp_threshold = ( cs1_ocp_limit 1.4 v/32) + 16 1.4/2 12 table 35. register 0x23cs2 gain trim bits bit name r/w description [7:6] reserved r/w reserved. 5 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [4:0] cs2 gain trim r/w this register calibrates the secondary side (cs2) current sense gain. it calibrates for errors in the sense resistor. see the cs2 trim section for more information. table 36. register 0x24cs2 analog offset trim bits bit name r/w description 7 reserved r/w reserved. 6 offset polarity r/w 1 = negative offset is introduced. 0 = positive offset is introduced. [5:0] cs2 offset trim r/w this register calibrates the secondary side (cs2) current sense common-mode error. it calibrates for errors in the resistor divider network. see the cs2 trim section for more information. table 37. register 0x25cs2 digital offset trim bits bit name r/w description [7:0] cs2 digital offset trim r/w this register contains the cs2 digital trim level. this value is used to calibrate the cs2 value that is read in register 0x18. see the cs2 trim section for more information. table 38. register 0x26cs2 accurate ocp limit bits bit name r/w description [7:0] cs2 accurate ocp r/w this register sets the cs2 accurate ocp current level. this 8-bit number is compared to the cs2 value register (register 0x18). when the cs2 value regist er is greater than the value in this register, the cs2 accurate ocp flag is set. the following equation gives the cs2 accurate ocp threshold: cs2_ocp_threshold = cs2_ocp_limit ( adc_range )/256 + 16 ( adc_range )/2 12 data sheet adp1046a rev. 0 | page 55 of 88 table 39. register 0x27 cs1/cs2 f ast ocp settings bits bit name r/w description [7:6] cs1 fast ocp debounce r/w these bits set the cs1 fast ocp debounce value. this is the minimum time that th e cs1 signal must be constantly above the fast ocp limit before the pwm outputs are shut down. when this happens, all pwm outputs are disabled for the remainder of the switching cycle. bit 7 bit 6 debounce (ns) 0 0 0 0 1 40 1 0 80 1 1 1 20 5 cs2 nominal voltage drop r/w these bits set the nominal full - scale voltage drop across the sense resistor. see the cs2 trim section for more information. these bits set the lsb step size of the cs2 adc. bit 5 adc range ( mv) lsb step size (v) 0 60 14.65 1 120 29.30 4 cs1 fast ocp bypass r/w setting this bit to 1 means that the flagin pin is used for cs1 fast ocp instead of the cs1 pin. 3 constant current mode r/w when this bit is set, constant current mode is en abled to 97% of the cs2 accurate ocp limit. 1 = constant current mode enabled. 0 = constant current mode disabled. 2 cs2 current sensing r/w this bit is set high if high - side current sensing is used. this bit is set low if low - side current sensing is used . see the cs2 trim section for more information. [1:0] cs1 fast ocp timeout r/w if the cs1 fast ocp comparator is set, all pwm outputs that are on at that time are immediately disabled for the remainder of the switching cycle. th e pwm outputs resume normal operation at the beginning of the next switching cycle. these bits set the number of consecutive switching cycles for the comparator before the cs1 fast ocp response is activated. bit 1 bit 0 number of switching cycles 0 0 1 0 1 62 1 0 188 1 1 440 table 40 . register 0x28 volt - second balance settings bits bit name r/w description 7 reserved r/w reserved. 6 volt - second balance enable r/w setting this bit enables volt - second balance fo r the main transformer (used for full - bridge configurations). for more information, see the volt - second balance section. 5 volt - second balance leading edge blanking r/w setting this bit means that cs1 is blanked f or volt - second balance calculations at the rising edge of th e pwm outputs that are selected for volt - second balance. the b lanking value is the same value configured for cs1 fast ocp blanking in register 0x22[7:5] . 4 volt - s econd disable during s oft s tart r /w 0 = d o not blank volt - second balance control during soft start . 1 = b lank volt - second balance control during soft start. 3 50% blanking of each phase r/w s etting this bit limits the sampling period for the current on cs1 to less than 50% of a half cycl e . 2 volt - second balance modulation r/w this bit specifies the maximum amount of modulation from volt - second balance . 0 = 80 ns maximum . 1 = 160 ns maximum . [1:0] volt - second balance gain setting r/w these bits set the gain of the volt - second balance c ircuit. the gain can be changed by a factor of 64. when these bits are set to 00, it takes approximately 700 ms to achieve volt - second balance. when these bits are set to 11, it takes approximately 10 ms to achieve volt - second balance. bit 1 bit 0 volt - second balance gain 0 0 1 0 1 4 1 0 16 1 1 64 adp1046a data sheet rev. 0 | page 56 of 88 table 41 . register 0x29 share bus bandwidth bits bit name r/w description [7:5] reserved r/w reserved. 4 bit stream r/w 1 = the current sense adc reading is output o n the shareo pin. this bit stream can be used for analog current sharing. 0 = the digital share bus signal is output on the shareo pin. this signal can be used for digital current sharing. 3 current share enable r/w 1 = reserved . 0 = cs2 reading used for current share. [2:0] share bus bandwidth r/w these bits determine the amount of bandwidth dedicated to the share bus. a value of 000 is the lowest possible bandwidth, and a value of 111 is the highest possible bandwidth. the slave is incremented by 1 lsb per share bus transaction (eight data bits plus start and stop bits). the master is decremented by n lsbs per share bus transaction, where n is the value of register 0x2a[7:4]. bit 2 bit 1 bit 0 bandwidth 0 0 0 d ivide lsb by 16 , that is, 1 lsb = 24 v/16 0 0 1 divide lsb by 8 0 1 0 divide lsb by 4 0 1 1 divide lsb by 2 1 0 0 nominal 1 0 1 multiply lsb by 2 1 1 0 multiply lsb by 4 1 1 1 multiply lsb by 8 table 42 . register 0x2a share bus setting b its bit name r/w description [7:4] number of bits dropped by master r/w these bits determine how much a master device reduces its output voltage to maintain current sharing. for more information, see the description of bits[2:0] in register 0x29. [3:0] b it difference between master and slave r/w these bits determine how closely a slave tries to match the current of the master device. the higher the setting, the larger the voltage difference that satisfies the current sharing criteria. table 43 . register 0x2b temperature gain trim bits bit name r/w description 7 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] gain trim r/w this register calibrates the rtd adc gain. it calibrates for error s in the adc. table 44 . register 0x2c pson/soft start bits bit name r/w description [7:6] ps_on setting r/w these bits determine which signal is used by the adp1046a as the ps_on con trol. bit 7 bit 6 ps_on setting 0 0 the adp1046a is always on. 0 1 hardware pson pin is used to enable or disable the power supply. 1 0 software ps_on bit (bit 5) is used to enable or disable th e power supply. 1 1 both the software ps_on bit and the hardware pson pin must be enabled before the adp1046a is enabled. 5 ps_on r/w software ps_on bit. 0 = power supply off. 1 = power supply on. [4:3] p s_on delay r/w these bits set the time from when the ps_on control signal is set to when the soft start begins. bit 4 bit 3 typical delay (sec) 0 0 0 0 1 0.5 1 0 1 1 1 2 data sheet adp1046a rev. 0 | page 57 of 88 bits bit name r/w description 2 reserved r/w set this bit to 0 for normal operation . 1 disable light load during soft start r/w 0 = allow switching to light load mode filter during soft start. 1 = never switch to light load mode filter during soft start . 0 force soft start filter r/w 0 = use normal mode filter or soft start filter , depending on th e orfet status. if regulating from vs3 (orfet on) , the n ormal mode f ilter is used . if regulating from vs1 (orfet off ), the soft start filter is used. 1 = use soft start filter as the initial filter regardless of orfet status . table 45 . register 0x2d pgood debounce and pin polarity setting s bits bit name r/w description [7:6] pgood1 turn - on debounce r/w th ese bits set the debounce time before the pgood1 pin and flag are set . th is debounce time starts at the end of the soft start ramp and can vary by 50 ms. the t urn - off of pgood1 is always immediate (no debounce). bit 7 bit 6 typical debounce time (ms) 0 0 350 0 1 150 1 0 550 1 1 0 [5:4] pgood2 turn - on debounce r/w these bits set the debounce time before the p good2 pin and flag are set. this debounce time starts at the end of the soft start ramp and can vary by 50 ms. the turn - off of pgood2 is always immediate (no debounce). bit 5 bit 4 typical debounce time (ms) 0 0 350 0 1 150 1 0 550 1 1 0 3 pgood2 flags r/w the following flags can also set the pgood2 pin: voltage continuity, orfet disable, acsns, flagin, and otp. this bit specifies whether these flags unconditionally set pgood2 or whether these flags set pgood2 only if the flag action i s not set to ignore in the appropriate fault configuration register (see table 12 and table 13). 0 = v oltage continuity, orfet disable, acsns, flagin, and otp flag s always set the pgood2 pin. 1 = v oltage continuity, orfet disable, acsns, flagin, and otp flag s set the pgood2 pin only if the flag action is not set to ignore. 2 flagin polarity r/w this bit sets the polarity of the flagin input pin: 1 = inverted (low = 0 v = on ). 1 gate polarity r/w this bit sets the polarity of the orfet gate control pin: 1 = inverted (low = 0 v = on). 0 pson polarity r/w this bit sets the polarity of the pson input pin: 1 = inverted (low = 0 v = on). table 46 . regis ter 0x2e modulation limit bits bit name r/w description 7 ful l - bridge mode r/w enable this bit when operating in full - bridge mode. it affects the modulation high limit. [6:0] modulation limit s r/w this value sets the min imum /max imum modulation limits re lative to the nominal edge value. the resolution depends on the switching frequency range. switching frequency range resolution corresponding to lsb 48.8 khz to 86.8 khz 160 ns 97.7 khz to 183.8 khz 80 ns 195 khz to 378.8 khz 40 ns 390. 6 khz to 625.0 khz 20 ns adp1046a data sheet rev. 0 | page 58 of 88 table 47 . register 0x2f otp threshold bits bit name r/w description [7:0] otp threshold r/w this register, adding 0 as the msb, results in a 9 - bit otp threshold value. this 9 - bit value is compared to t he nine msbs of the rtd adc reading. if the rtd adc reading is lower than the threshold set by these bits , the otp flag is set. this 8 - bit register provides 256 threshold setting s from 0 m v to 800 mv. one lsb equates to 800 mv/256 = 3.125 mv. some of the t hreshold settings at the high and low end s of the range are not allowed. the otp flag has a hysteresis of 16 mv. bit 7 bit 6 bit 3 bit 2 bit 1 bit 0 otp limit (mv) 0 0 0 0 0 0 0 0 0 0 0 0 1 3.125 0 0 0 0 1 0 6.25 0 0 0 0 1 1 9 .375 0 0 0 1 0 0 12.5 0 0 0 1 0 1 15. 62 5 1 1 1 0 0 1 778.125 1 1 1 0 1 0 781.25 1 1 1 1 1 1 796.875 table 48 . register 0x30 orfet bits bit name r/w description 7 orfet e nable delay r/w 0 = delay of 328 s, equivalent to 9 bits of ( vs1 ? vs2 ) data. 1 = delay of 164 s, equivalent to 8 bits of (vs1 ? vs2) data. [6:5] orfet enable threshold r/w these bits program the voltage difference between vs1 and vs2 before th e orfet is enabled. the vs1 and vs2 input pins are used to control the orfet enable function. bit 6 bit 5 adc full - scale voltage difference from vs1 to vs2 range (%) v out = 12 v (mv) v out = 48 v (mv) 0 0 ?2 ?384 ?1504 0 1 ?1 ?192 ?752 1 0 ?0.5 ?96 ?376 1 1 0 0 0 [4:2] fast orfet threshold r/w these bits program the threshold voltage difference between cs2+ and cs2? at which the orfet is disabled. the cs2+ and cs2? input pins are used to control this function. the internal circuit is an analog comparator. bit 4 bit 3 bit 2 voltag e difference from cs2+ to cs2? (mv) 0 0 0 ?3 0 0 1 ?6 0 1 0 ?9 0 1 1 ?12 1 0 0 ?15 1 0 1 ?18 1 1 0 ?21 1 1 1 ?24 1 fast orfet debounce r/w these bits determine the deboun ce on the fast orfet control before it disables the orfet. 0 = 40 ns. 1 = 200 ns. 0 fast orfet bypass r/w set this bit to completely bypass fast orfet control. the action programmed for the o r fet flag is executed, unless the flag is programmed to be ignor e d . data sheet adp1046a rev. 0 | page 59 of 88 voltage sense registers table 49. register 0x31vs3 volt age setting (remote voltage) bits bit name r/w description [7:0] vs3 voltage setting r/w this register is used to set the output voltage (voltage differential at the vs3+ and vs3? pins). each lsb corresponds to a 0.6% increase. setting this re gister to a value of 0xa0 gives an output voltage setting of 100% of the nominal voltage. this is the de fault value that is stored in this register when the part is shipped from the factory. updating the vs3 voltage setting is a two-stage process. the user must first change the value in this register; th is information is stored in a shadow register. to latch the new vs3 voltage setting into the state ma chine, the user must set the voltage reference go bit (register 0x7f[0]). after that, the voltage changes with a limited slew rate (programmed in register 0x5f[2:0]). table 50. register 0x32vs1 overvoltage limit (ovp) bits bit name r/w description [7:3] vs1 ovp setting r/w local overvoltage limit. this limit is progra mmable from 111.25% to 150% of the nominal vs1 voltage; 0x00 corresponds to 111.25%. each lsb re sults in an increase of 1.25%. the vs1 ovp threshold is calculated as follows: vs1_ovp_threshold = [(89 + vs1_ovp_setting )/128] 1.6 v for example, if the vs1 ovp setting is 10, then vs1_ovp_threshold = [(89 + 10)/128] 1.6 v = 1.2375 v setting these bits to 0 gives an ovp limit of 111.25% of the nominal vs1 voltage. setting these bits to 7 gives an ovp l imit of 120% of the nominal vs1 voltage. setting these bits to 15 gives an ovp limit of 130% of the nominal vs1 voltage. setting these bits to 31 gives an ovp limit of 150% of the nominal vs1 voltage. 2 reserved r/w reserved. [1:0] ovp sampling r/w the ovp flag is set if the average voltage during the ovp sampling period is greater than the ovp threshold. this ovp flag sampling period is 80 s. the number of samples can be increased using these bits. if the number of samples is increased, the average voltage must be greater than the ovp threshold for each of those cycles. for example, if this value is set to two cycles, the average voltage must be greater than the ovp threshold for both cycles. bit 1 bit 0 additional sampling (s) 0 0 0 (one sample sets the ovp flag) 0 1 80 (two samples set the ovp flag) 1 0 160 (three samples set the ovp flag) 1 1 240 (four samples set the ovp flag) table 51. register 0x33vs2 a nd vs3 overvoltage limit (ovp) bits bit name r/w description [7:3] vs2 and vs3 ovp setting r/w local overvoltage limit. this limit is progra mmable from 111.25% to 150% of the nominal vsx voltage; 0x00 corresponds to 111.25%. each lsb re sults in an increase of 1.25%. the vsx ovp threshold is calculated as follows: vsx_ovp_threshold = [(89 + vsx_ovp_setting )/128] 1.6 v for example, if the vs2 ovp setting is 10, then vs2_ovp_threshold = [(89 + 10)/128] 1.6 v = 1.2375 v setting these bits to 0 gives an ovp limit of 111.25% of the nominal vsx voltage. setting these bits to 7 gives an ovp limit of 120% of the nominal vsx voltage. setting these bits to 15 gives an ovp limit of 130% of the nominal vsx voltage. setting these bits to 31 gives an ovp limit of 150% of the nominal vsx voltage. 2 regulating point r/w when this bit is set, the adp1046a regulates from the vs3 node at all times. when this bit is not set, the adp1046a uses the vs1 voltage as the regulating poin t during soft start and when the orfet is disabled. adp1046a data sheet rev. 0 | page 60 of 88 bits bit name r/w description [1:0] ovp sampling r/w the ovp flag is set if the average voltage during the ovp samp ling period is greater than the ovp threshold. this ovp flag sampling period is 80 s. the number of samples can be increased using these bits. if the number of samples is increased, the average voltage must be greater than the ovp threshold for each of th ose cycles. for example, if this value is set to two cycles, the average voltage must be greater than the ovp threshold for both cycles. bit 1 bit 0 additional sampling (s) 0 0 0 (one sample sets the ovp flag) 0 1 80 (two samples set the ovp f lag) 1 0 160 (three samples set the ovp flag) 1 1 240 (four samples set the ovp flag) table 52 . register 0x34 vs1 undervoltage limit (uvp) bits bit name r/w description 7 end of cycle shutdown r/w this bit is valid only w hen the outaux pin is used for regulation. when any flag shuts down the power supply, the outaux pwm is immediately shut down. this bit specifies when the other pwm outputs are shut down. 1 = all other pwm outputs are shut down at the end of the switching cycle. 0 = all other pwm outputs are immediately shut down. [6:0] vs1 uvp setting r/w these bits set the uvp limit to one of 128 settings. the uvp limit can be programmed from 0% to 158.75% of the nominal vs1 voltage. each lsb increases the voltage by 158 .75%/128 = 1.25%. in reality, there are 81 usable settings, which program the uvp threshold from 0% to 100% of the nominal vs1 voltage. the vs1 uvp threshold is calculated as follows: vs1_uvp_threshold = [( vs1_uvp_setting + 1)/128] 1.6 v ? 12.5 mv for example, if the vs1 uvp setting is 60, then vs1_uvp_threshold = [(60 + 1)/128] 1.6 v ? 12.5 mv = 750 mv setting these bits to 0 gives a uvp limit of 0% of the nominal vs1 voltage. setting these bits to 72 (0x48) gives a uvp limit of 90% of the nominal vs1 voltage. setting these bits to 76 (0x4c) gives a uvp limit of 95% of the nominal vs1 voltage. setting these bits to 80 (0x50) gives a uvp limit of 100% of the nominal vs1 voltage. setting these bits to 127 (0x7f) gives a uvp limit of 158.75% of the nominal vs1 voltage. table 53 . register 0x35 line impedance limit bits bit name r/w description [7:0] line impedance limit r/w this value sets the threshold at which the line impedance flag is enabled. th is 8 - bit value is compared with the line impedance value (register 0x1f). if the line impedance value exceeds this value, the line impedance flag is set (register 0x02, bit 2). table 54 . register 0x36 load line impedance bits bit name r/w description 7 load line e nable r/w set this bit to enable the load line. [6:4] slew rate r/w these bits set the l oad line slew rate limit, which determines the maximum slew rate for changing the reference when adjusting the output load line valu e. bit 6 bit 5 bit 4 maximum slew rate duration 0 0 0 200 mv/ms 0 0 1 100 mv/ms 0 1 0 50 mv/ms 0 1 1 25 mv/ms 1 0 0 12.5 mv/ms 1 0 1 6.25 mv/ms 1 1 0 3.125 mv/ms 1 1 1 1.5625 mv/ms (4 lsb/ms) 3 reserved r/w reserved . data sheet adp1046a rev. 0 | page 61 of 88 bits bit name r/w description [ 2:0] load line setting r/w these bits specif y how much the output voltage decreases from nominal at full load . the amount of output resistance introduced can be calculated as follows (t hese bits specify the value of n ): r out = 0.1 v out_nom cs2 r sense /( cs2 range 2 n ) for more information, see the digital load line and slew rate section . bit 2 bit 1 bit 0 impedance setting 0 0 0 setting 0 0 0 1 setting 1 0 1 0 setting 2 0 1 1 setting 3 1 0 0 setting 4 1 0 1 setting 5 1 1 0 setting 6 1 1 1 setting 7 table 55. r egister 0x37 fast ovp comparator bits bit name r/w description [7:6] fast ovp debounce r/w th ese bits set the fast ovp debounce time . bit 7 b it 6 debounce time ( s) m in t yp m ax 0 0 0 0 0 0 1 0.64 0.96 1.28 1 0 1.92 2.24 2.56 1 1 7.98 8 8.32 [5:0] fast ovp threshold r/w these bits set the threshold for the fast ovp analog comparator. this threshold is programmable from 0. 8 v to 1.6 v. setting this value to 0x00 corresponds to a 0.8 v threshold. setting this value to 0x3f corresponds to a 1.6 v threshold. each lsb increments the threshold by 12.5 mv. the fast ovp threshold can be set using the following formula: fast_ ovp _th reshold = ( bits[5:0] 0.8 v/63) + 0.8 v table 56 . register 0x38 vs1 trim bits bit name r/w description 7 trim polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] vs1 trim r/w these bits set the amount of gain trim that is applied to the vs1 adc reading. this register trims the voltage at the vs1 pin for external resistor tolerances. when there is 1 v on the vs1 pin, this register is trimmed until the vs1 voltage value ( register 0x15[15:4] ) reads 2560 (0xa00). table 57 . register 0x39 vs2 trim bits bit name r/w description 7 trim polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] vs2 trim r/w these bits set the amount of gain trim that is applied to the vs2 adc reading. this register trims the voltage at the vs2 pin for external resistor tolerances. when there is 1 v on the vs2 pin, this register is trimmed until the vs2 voltage value ( register 0x16[15:4] ) reads 2560 (0xa00). table 58 . register 0x3a vs3 trim bits bit name r/w description 7 trim polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] vs3 trim r/w these bits set the amount of gain trim that is applied to the vs3 adc rea ding. this register trims the voltage at the vs3 pins for external resistor tolerances. when there is 1 v on each vs3 pin, this register is trimmed until the vs3 voltage value ( register 0x17[15:4] ) reads 2560 (0xa00). the vs3 trim must be performed before the load ovp and load uvp trims are performed. adp1046a data sheet rev. 0 | page 62 of 88 table 59 . register 0x3b light load mode disable setting s bits bit name r/w description 7 disable outaux r/w setting this bit means that outaux is also disabled if the load current fa lls below the light load sr disable threshold. 6 disable outd r/w setting this bit means that outd is also disabled if the load current falls below the light load sr disable threshold. 5 disable outc r/w setting this bit means that outc is also disabled if the load current falls below the light load sr disable threshold. 4 disable outb r/w setting this bit means that outb is also disabled if the load current falls below the light load sr disable threshold. 3 disable outa r/w setting this bit means that outa is also disabled if the load current falls below the light load sr disable threshold. [2:0] light load sr disable r/w these bits set the load current limit on the cs2 adc below which the synchronous rectifier outputs (sr1 and sr2) are disabled. this value also determines the point at which the power supply goes into light load mode and the light load mode filter is used. this value is programmable as a percentage of the cs2 adc full scale (either 60 mv or 120 mv). the hysteresis and the averaging spee d are programmable in register 0x7d. light load threshold as % of full scale bit 2 bit 1 bit 0 37.5 s 75 s 150 s 300 s 0 0 0 0% 0% 0% 0% 0 0 1 7.81% 3.91% 1.95% 0.98% 0 1 0 15.63% 7.81% 3.91% 1.95% 0 1 1 23.44% 11.72% 5.86% 2 .93% 1 0 0 31.25% 15.63% 7.81% 3.91% 1 0 1 39.06% 19.53% 9.77% 4.88% 1 1 0 46.88% 23.44% 11.72% 5.86% 1 1 1 54.69% 27.34% 13.67% 6.84% id registers table 60 . register 0x3c silicon revision id bits bit name r/w descr iption [7:0] silicon revision r this register contains the manufacturers silicon revision code for the device. this value is used by the manufacturer for tracking purposes. table 61 . register 0x3d manufacturer id bits bit name r /w description [7:0] manufacturer id code r this register contains the manufacturers id code for the device. it is used by the manufacturer for test purposes and should not be read from in normal operation. this value is hardwired to 0x41 to represent th e analog devices id code. table 62 . register 0x3e device id bits bit name r/w description [7:0] device id code r this register contains the id code for the device. this value is hardwired to 0x46 to represent the adp1046a . data sheet adp1046a rev. 0 | page 63 of 88 pwm and synchronous rectifier timing reg isters figure 57 and table 63 to table 93 describe the implementa tion and programming of the seven pwm signals that are output from the adp1046a . in general, it is recommended that t 1 be set to 0 and that t 1 be set as the reference point for the other signals. t period t period t 14 t 11 t 13 t 12 t 9 t 10 t 7 t 8 t 6 t 1 t 5 t 3 t 4 t 2 pwm5 (outaux) sync rect 2 (sr2) sync rect 1 (sr1) pwm4 (outd) pwm3 (outc) pwm2 (outb) pwm1 (outa) 1 1012-035 figure 57 . pwm timing diagram table 63 . register 0x3f outaux switching frequency setting bits bit name r/w description 7 pulse skipping r/w setting this bit enables pulse skipping mode. if the adp1046a requires a duty cycle lower than the modulation low limit, pulse skipping is enabled. 6 pulse skipping zero pwm r/w 0 = pulse skipping drives all modulated pwm outputs to 0 v . 1 = sets all modulated edges to t = 0 ( the cross ing rule set in register 0x52 [0] appl ies ) . [5:0] switching frequency r/w this register sets the switching frequency of the outaux signal. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frequency (khz) 0 0 0 0 0 0 48.83 0 0 0 0 0 1 50.40 0 0 0 0 1 0 5 2.08 0 0 0 0 1 1 53.88 0 0 0 1 0 0 55.80 0 0 0 1 0 1 57.87 0 0 0 1 1 0 60.1 0 0 0 1 1 1 62.5 0 0 1 0 0 0 65.1 0 0 1 0 0 1 67.93 0 0 1 0 1 0 71.02 0 0 1 0 1 1 74.4 0 0 1 1 0 0 78.13 0 0 1 1 0 1 82.24 0 0 1 1 1 0 86.81 0 0 1 1 1 1 91.91 0 1 0 0 0 0 97.66 0 1 0 0 0 1 100.81 0 1 0 0 1 0 104.17 adp1046a data sheet rev. 0 | page 64 of 88 bits bit name r/w description [5:0] switching frequency r/w bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frequency (khz) 0 1 0 0 1 1 107.76 0 1 0 1 0 0 111.61 0 1 0 1 0 1 115.74 0 1 0 1 1 0 120.19 0 1 0 1 1 1 125.0 0 1 1 0 0 0 130.21 0 1 1 0 0 1 135.87 0 1 1 0 1 0 142.05 0 1 1 0 1 1 148.81 0 1 1 1 0 0 156.25 0 1 1 1 0 1 164.47 0 1 1 1 1 0 173.61 0 1 1 1 1 1 183.82 1 0 0 0 0 0 195.31 1 0 0 0 0 1 201.61 1 0 0 0 1 0 208.33 1 0 0 0 1 1 215.52 1 0 0 1 0 0 223.21 1 0 0 1 0 1 231.48 1 0 0 1 1 0 240.38 1 0 0 1 1 1 250 1 0 1 0 0 0 260.42 1 0 1 0 0 1 271.42 1 0 1 0 1 0 284.09 1 0 1 0 1 1 297.62 1 0 1 1 0 0 312.5 1 0 1 1 0 1 328.95 1 0 1 1 1 0 347.22 1 0 1 1 1 1 367.65 1 1 0 0 0 0 390.63 1 1 0 0 0 1 416.67 1 1 0 0 1 0 446.43 1 1 0 0 1 1 480.77 1 1 0 1 0 0 520.83 1 1 0 1 0 1 568.18 1 1 0 1 1 0 625 data sheet adp1046a rev. 0 | page 65 of 88 table 64 . register 0x40 pwm switching frequency setting bits bit name r/w description [7:6] reserved r/w reserved. [5:0] switching frequency r/w this register sets the switching frequency of all the pwm pins other than the outaux pin. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frequency (khz) 0 0 0 0 0 0 48.83 0 0 0 0 0 1 50.40 0 0 0 0 1 0 52.08 0 0 0 0 1 1 53.88 0 0 0 1 0 0 55.80 0 0 0 1 0 1 57.87 0 0 0 1 1 0 60.1 0 0 0 1 1 1 62.5 0 0 1 0 0 0 65.1 0 0 1 0 0 1 67. 93 0 0 1 0 1 0 71.02 0 0 1 0 1 1 74.4 0 0 1 1 0 0 78.13 0 0 1 1 0 1 82.24 0 0 1 1 1 0 86.81 0 0 1 1 1 1 91.91 0 1 0 0 0 0 97.66 0 1 0 0 0 1 100.81 0 1 0 0 1 0 104.17 0 1 0 0 1 1 107.76 0 1 0 1 0 0 111.61 0 1 0 1 0 1 115.74 0 1 0 1 1 0 120.19 0 1 0 1 1 1 125.0 0 1 1 0 0 0 130.21 0 1 1 0 0 1 135.87 0 1 1 0 1 0 142.05 0 1 1 0 1 1 148.81 0 1 1 1 0 0 156.25 0 1 1 1 0 1 164.47 0 1 1 1 1 0 173.61 0 1 1 1 1 1 183.82 1 0 0 0 0 0 195.31 1 0 0 0 0 1 201.61 1 0 0 0 1 0 208.33 1 0 0 0 1 1 215.52 1 0 0 1 0 0 223.21 1 0 0 1 0 1 231.48 1 0 0 1 1 0 240.38 1 0 0 1 1 1 250 1 0 1 0 0 0 260.42 1 0 1 0 0 1 271.42 1 0 1 0 1 0 284.09 1 0 1 0 1 1 29 7.62 1 0 1 1 0 0 312.5 1 0 1 1 0 1 328.95 1 0 1 1 1 0 347.22 1 0 1 1 1 1 367.65 1 1 0 0 0 0 390.63 adp1046a data sheet rev. 0 | page 66 of 88 bits bit name r/w description [5:0] switching frequency r/w bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frequency (khz) 1 1 0 0 0 1 416.67 1 1 0 0 1 0 446.43 1 1 0 0 1 1 480.77 1 1 0 1 0 0 520.83 1 1 0 1 0 1 568.18 1 1 0 1 1 0 625 1 1 1 1 1 1 resonant mode table 65 . register 0x41 outa rising edge timing (outa pin) bits bit name r/w description [7:0] t 1 r/w this register co ntains the eight msbs of the 12 - bit t 1 time. this value is always used with the top four bits of register 0x42, which contains the four lsbs of the t 1 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time ste ps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step , the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps , the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. table 66 . register 0x42 outa rising edge setting (outa pin) bits bit name r/w description [7:4] t 1 r/w these bits contain the four lsbs of the 12 - bit t 1 time. this value is always used with the eight bits of register 0x41, which co ntains the eight msbs of the t 1 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x o ccur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. 3 modulate enable r/w 1 = pwm modulation acts on the t 1 edge. 0 = no pwm modulation of the t 1 edge. 2 t 1 sign r/w 1 = negative sign. increase of pwm modulation moves t 1 right. 0 = positive sign. increase of pwm modulation moves t 1 left. 1 reserved r/w reserved. 0 volt - second balance source selection r/w if this bit is set to 1 , the outa rising edge is selected as the st art of the integration period for volt - second balance . table 67 . register 0x43 outa falling edge timing (outa pin) bits bit name r/w description [7:0] t 2 r/w this register contains the eight msbs of the 12 - bit t 2 time. this value is always used with the top four bits of register 0x44, which contains the four lsbs of the t 2 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the s ame 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. table 68 . register 0x44 outa falling edge setting (outa pin) bits bit name r/w description [7:4] t 2 r/w these bits contain the four lsbs of the 12 - bit t 2 time. this value is always used with the eight bits of register 0x 43, which contains the eight msbs of the t 2 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. 3 modulate enable r/w 1 = pwm modulation acts on the t 2 edge. 0 = no pwm modulation of the t 2 edge. 2 t 2 sign r/w 1 = negative sign. increase of pwm modulation moves t 2 right. 0 = positive sign. increase of pwm modulation moves t 2 left. [1:0] r eserved r/w reserved. data sheet adp1046a rev. 0 | page 67 of 88 table 69 . register 0x45 outb rising edge timing (outb pin) bits bit name r/w description [7:0] t 3 r/w this register contains the eight msbs of the 12 - bit t 3 time. this value is always used with the top four bits of register 0x46, which contains the four lsbs of the t 3 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm outpu t is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. table 70 . register 0x46 outb rising edge setting (outb pin) bits bit name r/w description [7:4] t 3 r/w these bits contain the four lsbs of the 12 - bit t 3 time. this value is always used with the eight bits of register 0x45, which contains the eight msbs of the t 3 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the ab solute maximum pulse width is t period ? 5 ns. 3 modulate enable r/w 1 = pwm modulation acts on the t 3 edge. 0 = no pwm modulation of the t 3 edge. 2 t 3 sign r/w 1 = negative sign. increase of pwm modulation moves t 3 right. 0 = positive sign. increase of p wm modulation moves t 3 left. 1 reserved r/w reserved. 0 volt - second balance source selection r/w if this bit is set to 1, the outb rising edge is selected as the start of the integration period for volt - second balance. table 71. register 0x47 outb falling edge timing (outb pin) bits bit name r/w description [7:0] t 4 r/w this register contains the eight msbs of the 12 - bit t 4 time. this value is always used with the top four bits of register 0x48, which contains the four lsbs of t he t 4 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns ti me steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. table 72 . register 0x48 outb falling edge setting (outb pin) bits bit name r/w description [7:4] t 4 r/w these bits contain the four lsbs of the 12 - bit t 4 time. this value is always used with the eight bits of register 0x 47, which contains the eight msbs of the t 4 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. 3 modulate enable r/w 1 = pwm modulation acts on the t 4 edge. 0 = no pwm modulation of the t 4 edge. 2 t 4 sign r/w 1 = negative sign. increase of pwm modulation moves t 4 right. 0 = positive sign. increase of pwm modulation moves t 4 left. [1:0] r eserved r/w reserved. table 73 . register 0x49 outc rising edge timing (outc pin) bits bit name r/w description [7:0] t 5 r/w this register contains the eight msbs of the 12 - bit t 5 time. this value is always used with the top four bits of register 0x4a, which contains the four lsbs of the t 5 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm outpu t is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. adp1046a data sheet rev. 0 | page 68 of 88 table 74 . register 0x4a outc rising edge setting (outc pin) bits bit name r/w description [7:4] t 5 r/w these bits contain the four lsbs of the 12 - bit t 5 time. this value is always used with the eight bits of register 0x49, which contains the eight msbs of the t 5 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the ab solute maximum pulse width is t period ? 5 ns. 3 modulate enable r/w 1 = pwm modulation acts on the t 5 edge. 0 = no pwm modulation of the t 5 edge. 2 t 5 sign r/w 1 = negative sign. increase of pwm modulation moves t 5 right. 0 = positive sign. increase of p wm modulation moves t 5 left. 1 reserved r/w reserved. 0 volt - second balance source selection r/w if this bit is set to 1, the outc rising edge is selected as the start of the integration period for volt - second balance. table 75. register 0x4b outc falling edge timing (outc pin) bits bit name r/w description [7:0] t 6 r/w this register contains the eight msbs of the 12 - bit t 6 time. this value is always used with the top four bits of register 0x4c, which contains the four lsbs of t he t 6 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns ti me steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. table 76 . register 0x4c outc falling edge setting (outc pin) bits bit name r/w description [7:4] t 6 r/w these bits contain the four lsbs of the 12 - bit t 6 time. this value is always used with the eight bits of register 0x 4b, which contains the eight msbs of the t 6 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. 3 modulate enable r/w 1 = pwm modulation acts on the t 6 edge. 0 = no pwm modulation of the t 6 edge. 2 t 6 sign r/w 1 = negative sign. increase of pwm modulation moves t 6 right. 0 = positive sign. increase of pwm modulation moves t 6 left. [1:0] r eserved r/w reserved. table 77 . register 0x4d outd rising edge timing (outd pin) bits bit name r/w description [7:0] t 7 r/w this register contains the eight msbs of the 12 - bit t 7 time. this value is always used with the top four bits of register 0x4e, which contains the four lsbs of the t 7 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm outpu t is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. data sheet adp1046a rev. 0 | page 69 of 88 table 78 . register 0x4e outd rising edge setting (outd pin) bits bit name r/w description [7:4] t 7 r/w these bits contain the four lsbs of the 12 - bit t 7 time. this value is always used with the eight bits of register 0x4d, which contains the eight msbs of the t 7 time. each lsb corresponds to 5 ns resolution. the entir e switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the a bsolute maximum pulse width is t period ? 5 ns. 3 modulate enable r/w 1 = pwm modulation acts on the t 7 edge. 0 = no pwm modulation of the t 7 edge. 2 t 7 sign r/w 1 = negative sign. increase of pwm modulation moves t 7 right. 0 = positive sign. increase of pwm modulation moves t 7 left. 1 reserved r/w reserved. 0 volt - second balance source selection r/w if this bit is set to 1, the outd rising edge is selected as the start of the integration period for volt - second balance. table 79 . register 0x4f outd falling edge timing (outd pin) bits bit name r/w description [7:0] t 8 r/w this register contains the eight msbs of the 12 - bit t 8 time. this value is always used with the top four bits of register 0x50, which contains the four lsbs of the t 8 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns t ime steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. table 80 . register 0x50 outd falling edge setting (outd pin) bits bit name r/w description [7:4] t 8 r/w these bits contain the four lsbs of the 12 - bit t 8 time. this value is always used with the eight bits of register 0x 4f, which contains the eight msbs of the t 8 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. 3 modulate enable r/w 1 = pwm modulation acts on the t 8 edge. 0 = no pwm modulation of the t 8 edge. 2 t 8 sign r/w 1 = negative sign. increase of pwm modulation moves t 8 right. 0 = positive sign. increase of pwm modulation moves t 8 left. [1:0] r eserved r/w reserved. table 81 . register 0x51 sr1 rising edge timing (sr1 pin) bits bit name r/w description [7:0] t 9 r/w this register contains the eight msbs of the 12 - bit t 9 time. this value is always used with the top four bi ts of register 0x52, which contains the four lsbs of the t 9 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. it is recommended that the sr1 rising edge not be set between 80 ns and 115 ns when using the sr soft start. adp1046a data sheet rev. 0 | page 70 of 88 table 82 . register 0x52 sr1 rising edge setting (sr1 pin) bits bit name r/w description [7:4] t 9 r/w these bits contain the four lsbs of the 12 - bit t 9 time. this value is always used with the eight bits of regist er 0x51, which contains the eight msbs of the t 9 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. it is recommended that the sr1 rising edge not be set between 80 ns and 115 ns wh en using the sr soft st art. 3 modulate enable r/w 1 = pwm modulation acts on the t 9 edge. 0 = no pwm modulation of the t 9 edge. 2 t 9 sign r/w 1 = negative sign. increase of pwm modulation moves t 9 right. 0 = positive sign. increase of pwm modulation moves t 9 left. 1 reserved r/w reserved. 0 sr soft start e dge control r/w 0 = always allow sr edge crossing. 1 = allow sr edge crossing only during sr soft start (recommended). table 83 . register 0x53 sr1 falling edge timing (sr1 pin) bits bit name r/w des cription [7:0] t 10 r/w this register contains the eight msbs of the 12 - bit t 10 time. this value is always used with the top four bits of register 0x54, which contains the four lsbs of the t 10 time. each lsb corresponds to 5 ns resolution. the entire switc hing period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. table 84 . register 0x54 sr1 falling edge setting (sr1 pin) bits bit name r/w description [7:4] t 10 r/w these bits contain the four lsbs of the 12 - bit t 10 time. this value is always used wit h the eight bits of register 0x53, which contains the eight msbs of the t 10 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. 3 modulate enable r/w 1 = pwm modulation acts on the t 10 edge. 0 = no pwm modulation of the t 10 edge. 2 t 10 sign r/w 1 = negative sign. increase of pwm modulation moves t 10 right. 0 = positive sign. increase of pwm modulation moves t 10 left. 1 sr soft start setting r/w 1 = sr signals perform a soft start every time that they are enabled. 0 = sr signals perform a soft start only the first time that they are enabled. 0 sr soft start enable r/w setting this bit enables the soft start function for the sr signals. table 85 . register 0x55 sr2 rising edge timing (sr2 pin) bits bit name r/w description [7:0] t 11 r/w this register contains the eight msbs of the 12 - bit t 11 time. this value is always used with the top four bits o f register 0x56, which contains the four lsbs of the t 11 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns . it is recommended that the sr2 rising edge not be set between 80 ns and 115 ns when using the sr soft start. data sheet adp1046a rev. 0 | page 71 of 88 table 86 . register 0x56 sr2 rising edge setting (sr2 pin) bits bit name r/w description [7:4] t 11 r/w these bi ts contain the four lsbs of the 12 - bit t 11 time. this value is always used with the eight bits of register 0x55, which contains the eight msbs of the t 11 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. it is recommended that the sr2 rising edge not be set between 80 ns and 115 ns when using the sr soft start. 3 modulate enable r/w 1 = pwm modulation acts on the t 11 edge. 0 = no pwm modulation of the t 11 edge. 2 t 11 sign r/w 1 = negative sign. increase of pwm modulation moves t 11 right. 0 = positive sign. increase of pwm modulation moves t 11 left. [1:0] reserved r/w reserved. table 87 . register 0x57 sr2 falling edge timing (sr2 pin) bits bit name r/w description [7:0] t 12 r/w this register contains the eight msbs of the 12 - bit t 12 time. this value is always used with the top four bits of register 0x58, which contains the four lsbs of the t 12 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. table 88 . register 0x58 sr2 falling edge setting (sr2 pin) bits bit name r/w description [7:4] t 12 r/w these bits contain the four lsbs of the 12 - bit t 12 time. this value is always used with the eight bits of register 0 x57, which contains the eight msbs of the t 12 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t f x of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t f x occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. 3 modulate enable r/w 1 = pwm modulation acts on the t 12 edge. 0 = no pwm modulation of the t 12 edge. 2 t 12 sign r/w 1 = negative sign. increase of pwm modulation moves t 12 right. 0 = positive sign. increase of pwm modulation moves t 12 left. [1 :0] reserved r/w reserved. table 89 . register 0x59 outaux rising edge timing (outaux pin) bits bit name r/w description [7:0] t 13 r/w this register contains the eight msbs of the 12 - bit t 13 time. this value is always used with th e top four bits of register 0x5a, which contains the four lsbs of the t 13 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t fx of a pwm edge occur within the same 40 ns time step, t he pwm output is 0 v. if the t rx and t fx occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. d epending on the switching frequency and the outaux frequency , there is a const ant lag/lead time between this edge and the other edges (t 1 to t 12 ); therefore, outaux is not synchronized to the other pwm outputs but can be made synchronous by adjusting the delay accordingly. if either the outaux switching frequency (register 0x3f) or the pwm switching frequency (register 0x40) is changed after edge adjustment, the synchroniza - tion between outaux and the pwm edges is no longer maintained. the outaux delay must be adjusted again to synchronize the edges to the pwm edges for the new set o f switching frequencies. adp1046a data sheet rev. 0 | page 72 of 88 table 90 . register 0x5a outaux rising edge setting (outaux pin) bits bit name r/w description [7:4] t 13 r/w these bits contain the four lsbs of the 12 - bit t 13 time. this value is always used with the eig ht bits of register 0x59, which contains the eight msbs of the t 13 time. each lsb corresponds to 5 ns resolution. the entire switching period i s divided into 40 ns time steps . if the t rx and t fx of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t fx occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. depending on the switching frequency and the outaux frequency, there is a constant lag /lead time between this edge and the other edges (t 1 to t 12 ); therefore, outaux is not synchronized to the other pwm outputs but can be made synchronous by adjusting the delay accordingly. if either the outaux switching frequency (register 0x3f) or the pwm switching frequency (register 0x40) is changed after edge adjustment, the synchroniza - tion between outaux and the pwm edges is no longer maintained. the outaux delay must be adjusted again to synchronize the edges to the pwm edges for the new set of switc hing frequencies. 3 modulate enable r/w 1 = pwm modulation acts on the t 13 edge. 0 = no pwm modulation of the t 13 edge. 2 t 13 sign r/w 1 = negative sign. increase of pwm modulation moves t 13 right. 0 = positive sign. increase of pwm modulation moves t 13 left. [1:0] reserved r/w reserved. table 91 . register 0x5b outaux falling edge timing (outaux pin) bits bit name r/w description [7:0] t 14 r/w this register contains the eight msbs of the 12 - bit t 14 time. this value is always us ed with the top four bits of register 0x5c, which contains the four lsbs of the t 14 time. each lsb corresponds to 5 ns resolution. the entire switching period is divided into 40 ns time steps. if the t rx and t fx of a pwm edge occur within the same 40 ns ti me step, the pwm output is 0 v. if the t rx and t fx occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. depending on the switching frequency and the outaux frequency, there is a constant lag/lead time between this edge and the other edges (t 1 to t 12 ); therefore, outaux is not synchronized to the other pwm outputs but can be made synchronous by adjus ting the delay accordingly. if either the outaux switching frequency (register 0x3f) or the pwm switching frequency (register 0x40) is changed after edge adjustment, the synchroniza - tion between outaux and the pwm edges is no longer maintained. the outaux delay must be adjusted again to synchronize the edges to the pwm edges for the new set of switching frequencies. table 92 . register 0x5c outaux falling edge setting (outaux pin) bits bit name r/w description [7:4] t 14 r/w these b its contain the four lsbs of the 12 - bit t 1 4 time. this value is always used with the eight bits of register 0x5 b , which contains the eight msbs of the t 1 4 time. each lsb corresponds to 5 ns resolution. the entire switching period i s divided into 40 ns time steps . if the t rx and t fx of a pwm edge occur within the same 40 ns time step, the pwm output is 0 v. if the t rx and t fx occur in different 40 ns time steps, the pwm output is set to the programmed value. the absolute maximum pulse width is t period ? 5 ns. depending on the switching frequency and the outaux frequency, there is a constant lag/lead time between this edge and the other edges (t 1 to t 12 ); therefore, outaux is not synchronized to the other pwm outputs but can be made synchronous by adjus ting the delay accordingly. if either the outaux switching frequency (register 0x3f) or the pwm switching frequency (register 0x40) is changed after edge adjustment, the synchroniza - tion between outaux and the pwm edges is no longer maintained. the outaux delay must be adjusted again to synchronize the edges to the pwm edges for the new set of switching frequencies. 3 modulate enable r/w 1 = pwm modulation acts on the t 14 edge. 0 = no pwm modulation of the t 14 edge. 2 t 14 sign r/w 1 = negative sign. incre ase of pwm modulation moves t 14 right. 0 = positive sign. increase of pwm modulation moves t 14 left. 1 regulate with outaux r/w 1 = control loop pwm modulation is regulated by outaux. when this bit is set, the cs1 blanking signal is synchronized with outa ux. 0 = control loop pwm modulation is regulated by outa, outb, outc, outd, sr1, and sr2 (normal mode). note tha t a write to this bit immediately switch es the regulation point and frequency settings ; h owever, the correct modulation limit and filter setting s do not take effect until a subsequent f req uency go is executed using register 0x7f[ 2 ]. for this reason , it is not recommended that the regulation point be changed on the fly using r egister 0x5c[1]. 0 reserved r/w reserved. set this bit to 0 for normal o peration. data sheet adp1046a rev. 0 | page 73 of 88 table 93 . register 0x5d outx and srx pin disable setting s bits bit name r/w description 7 outaux disable r/w setting this bit disables the outaux output. 6 sr2 disable r/w setting this bit disables the sr2 output. 5 s r1 disable r/w setting this bit disables the sr1 output. 4 outd disable r/w setting this bit disables the outd output. 3 outc disable r/w setting this bit disables the outc output. 2 outb disable r/w setting this bit disables the outb output. 1 outa di sable r/w setting this bit disables the outa output. 0 gate disable r/w setting this bit disables the ga te output but does not affect the vsx feedback point. table 94 . register 0x5e acsns gain trim bits bit name r/w description 7 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] acsns gain trim r/w these bits set the g ain trim for the acsns adc . digital filter progr amming registers register 0x5f to register 0x67 can be used to program th e digital filters. it is recommended that the software gui be used to program the digital filters. pole location range zero zero range 20db pole lf gain range 20db 20db hf gain range 100hz 500hz 1khz 5khz 10khz 11012-036 figure 58 . digital filter programmability table 95. register 0x5f soft start and output voltage slew rate setting s bits bit name r/w description [7:5] soft start ramp r/w these bits determine the duration of the soft start ramp . bit 7 bit 6 bit 5 ramp duration 0 0 0 5 ms 0 0 1 10 ms 0 1 0 15 ms 0 1 1 20 ms 1 0 0 40 ms 1 0 1 50 ms 1 1 0 80 ms 1 1 1 100 ms 4 soft start from precharge r/w setting this bit to 1 e nables the soft start from precharge function. when this function is enabled, the s oft start ramp starts from the value of the voltage detected on vs1 or vs3 (dependi ng on the orfet status) . 3 reserved r/w reserved. adp1046a data sheet rev. 0 | page 74 of 88 bits bit name r/w description [2:0] slew rate r/w these bits specify the slew rate at the vs3 pins for the change in the v oltage reference setting . bit 2 bit 1 bit 0 slew ra te 0 0 0 200 mv/ms 0 0 1 100 mv/ms 0 1 0 50 mv/ms 0 1 1 25 mv/ms 1 0 0 12.5 mv/ms 1 0 1 6.25 mv/ms 1 1 0 3.125 mv/ms 1 1 1 1.5625 mv/ms (4 lsb/ms) table 96 . register 0x60 normal mode digital filter lf gain setting bits bit name r/w description [7:0] lf gain setting r/w this register determines the low frequency gain of the loop response in normal mode . the lf gain is p r ogrammable over a 20 db range (s ee figure 58). table 97 . register 0x 61 normal mode digital filter zero setting bits bit name r/w description [7:0] zero setting r/w this register determines the position of the final zero in normal mode (s ee figure 58). table 98 . register 0x62 normal mode digital filter pole setting bits bit name r/w description [7:0] pole location r/w this register determines the position of the final pole in normal mode (s ee figure 58). table 99 . register 0x63 normal mode digital filter hf gain setting bits bit name r/w description [7:0] hf gain setting r/w this register determines the high frequency gain of the loop response in normal mode . the hf gain is programmable ov er a 20 db range (s ee figure 58). table 100 . register 0x64 light load mode digital filter lf gain setting bits bit name r/w description [7:0] lf gain setting r/w this register determines the low frequency gain of the loop response in light load mode . the lf gain is programmable over a 20 db range (see figure 58). table 101 . register 0x65 light load mode digital filter zero setting bits bit name r/w description [7:0] zero setting r/w this register determines the position of the final zero in light load mode (s ee figure 58). table 102 . register 0x66 light lo ad mode digital filter pole setting bits bit name r/w description [7:0] pole location r/w this register determines the position of the final pole in light load mode (s ee figure 58). table 103 . register 0x67 light load mode digital filter hf gain setting bits bit name r/w description [7:0] hf gain setting r/w this register determines the high frequency gain of the loop response in light load mode . the hf gain is programmable over a 20 db r ange (see figure 58). table 104 . register 0x6 8 reserved bits bit name r/w description [7:0] reserved r/w set these bits to 0x00 for proper operation. data sheet adp1046a rev. 0 | page 75 of 88 soft start filter pr ogramming regis ters table 105 . register 0x71 soft start digital filter lf gain setting bits bit name r/w description [7:0] lf gain setting r/w this register determines the low frequency gain of the loop response during soft start . the lf gain is programmable over a 20 db range (see figure 58). table 106 . register 0x72 soft start digital filter zero setting bits bit name r/w description [7:0] zero setting r/w this register determi nes the position of the final zero during soft start (s ee figure 58). table 107 . register 0x73 soft start digital filter pole setting bits bit name r/w description [7:0] pole location r/w this register determines the position of the final pole during soft start (s ee figure 58). table 108 . register 0x74 soft start digital filter hf gain setting bits bit name r/w description [7:0] hf gain setting r/w this register determines the high frequency gain of the loop response during soft start . the hf gain is programmable over a 20 db range (see figure 58). extended functions r egisters ta ble 109 . register 0x75 voltage line feedf orward bits bit name r/w description [7:4] reserved r/w reserved. 3 disable feedfor ward during soft start r/w if voltage line feedforward is enabled, this bit disable s it during the referen c e ramp - up (soft start). this operation is gated by the filter go bit (register 0x7f[3]). 0 = feedforward enabled during soft start (recommended setting). 1 = feedforward disabled during soft start . 2 feedfor ward enable r/w this bit e nables the voltage li ne feedf or ward loop. this operation is gated by the filter go bit (register 0x7f[3]). 0 = feedforward disabled. 1 = feedforward enabled. [1:0] gain setting r/w these bits set the gain for the voltage feedf or ward function . bit 1 bit 0 gain 0 0 1 0 1 0.875 1 0 0.75 1 1 0.5 table 110 . register 0x76 volt - second balance settings ( outa and outb pins) bits bit name r/w description 7 modulate enable, t 1 r/w setting this bit enables modulation from balance control on t he outa rising edge, t 1 . it is recommended that volt - second balance not be enabled on edges that are between 0 ns and 640 ns of the switching period. 6 t 1 sign r/w 0 = p ositive sign. increase of balance control modulation moves t 1 right. 1 = n egative sign . increase of balance control modulation moves t 1 left. 5 modulate enable, t 2 r/w setting this bit enables modulation from balance control on the outa falling edge, t 2 . it is recommended that volt - second balance not be enabled on edges that are between 0 ns and 640 ns of the switching period. 4 t 2 sign r/w 0 = p ositive sign. increase of balance control modulation moves t 2 right. 1 = n egative sign. increase of balance control modulation moves t 2 left. 3 modulate enable, t 3 r/w setting this bit enables mod ulation from balance control on the outb rising edge, t 3 . it is recommended that volt - second balance not be enabled on edges that are between 0 ns and 640 ns of the switching period. adp1046a data sheet rev. 0 | page 76 of 88 bits bit name r/w description 2 t 3 sign r/w 0 = p ositive sign. increase of balance control modulation moves t 3 right. 1 = n egative sign. increase of balance control modulation moves t 3 left. 1 modulate enable, t 4 r/w setting this bit enables modulation from balance control on the outb falling edge, t 4 . it is recommended that volt - second balance not be enabled on edges that are between 0 ns and 640 ns of the switching period. 0 t 4 sign r/w 0 = p ositive sign. increase of balance control modulation moves t 4 right. 1 = n egative sign. increase of balance co ntrol modulation moves t 4 left. table 111 . register 0x77 volt - second balance settings ( outc and outd pins) bits bit name r/w description 7 modulate enable, t 5 r/w setting this bit enables modulation from balance control on the ou tc rising edge, t 5 . it is recommended that volt - second balance not be enabled on edges that are between 0 ns and 640 ns of the switching period. 6 t 5 sign r/w 0 = p ositive sign. increase of balance control modulation moves t 5 right. 1 = n egative sign. inc rease of balance control modulation moves t 5 left. 5 modulate enable, t 6 r/w setting this bit enables modulation from balance control on the outc falling edge, t 6 . it is recommended that volt - second balance not be enabled on edges that are between 0 ns an d 640 ns of the switching period. 4 t 6 sign r/w 0 = p ositive sign. increase of balance control modulation moves t 6 right. 1 = n egative sign. increase of balance control modulation moves t 6 left. 3 modulate enable, t 7 r/w setting this bit enables modulati on from balance control on the outd rising edge, t 7 . it is recommended that volt - second balance not be enabled on edges that are between 0 ns and 640 ns of the switching period. 2 t 7 sign r/w 0 = p ositive sign. increase of balance control modulation moves t 7 right. 1 = n egative sign. increase of balance control modulation moves t 7 left. 1 modulate enable, t 8 r/w setting this bit enables modulation from balance control on the outd falling edge, t 8 . it is recommended that volt - second balance not be enabled on edges that are between 0 ns and 640 ns of the switching period. 0 t 8 sign r/w 0 = p ositive sign. increase of balance control modulation moves t 8 right. 1 = n egative sign. increase of balance control modulation moves t 8 left. table 112 . register 0x78 volt - second balance settings ( sr1 and sr2 pins) bits bit name r/w description 7 modulate enable, t 9 r/w setting this bit enables modulation from balance control on the sr1 rising edge, t 9 . it is recommended that volt - second balance not be enabled on edges that are between 0 ns and 640 ns of the switching period. 6 t 9 sign r/w 0 = p ositive sign. increase of balance control modulation moves t 9 right. 1 = n egative sign. increase of balance control modulation moves t 9 left. 5 modulate enable, t 10 r/w setting this bit enables modulation from balance control on the sr1 falling edge, t 10 . it is recommended that volt - second balance not be enabled on edges that are between 0 ns and 640 ns of the switching period. 4 t 10 sign r/w 0 = p ositiv e sign. increase of balance control modulation moves t 10 right. 1 = n egative sign. increase of balance control modulation moves t 10 left. 3 modulate enable, t 1 1 r/w setting this bit enables modulation from balance control on the sr2 rising edge, t 11 . it i s recommended that volt - second balance not be enabled on edges that are between 0 ns and 640 ns of the switching period. 2 t 11 sign r/w 0 = p ositive sign. increase of balance control modulation moves t 11 right. 1 = n egative sign. increase of balance contr ol modulation moves t 11 left. 1 modulate enable, t 12 r/w setting this bit enables modulation from balance control on the sr2 falling edge, t 12 . it is recommended that volt - second balance not be enabled on edges that are between 0 ns and 640 ns of the swit ching period. 0 t 12 sign r/w 0 = p ositive sign. increase of balance control modulation moves t 12 right. 1 = n egative sign. increase of balanc e control modulation moves t 12 left. data sheet adp1046a rev. 0 | page 77 of 88 table 113 . register 0x79 sr delay compensation bit s bit name r/w description [7:6] reserved r/w reserved. [ 5:0 ] sr driver delay r/w these bits specify the 6 - bit representation of the sr delay in steps of 5 ns . 000000 = 0 ns . 111111 = 63 ns 5 ns = 315 ns . table 114 . register 0 x7a filter transition s bits bit name r/w description [7:6] reserved r/w reserved . [5:3] hf adc configuration r/w set these bits to 001 at all times for proper operation. 2 enable soft transition r/w setting this bit e nables a soft transition between fil ter settings to minimize output transients. all four parameters of each filter are linearly transitioned to the new value. [1:0] transition speed r/w these bits set the transition speed from one filter to another. the filter changes in 32 steps ; each step is applied at the multiple of switching cycles (t sw ) specified by these bits. bit 1 bit 0 speed (t sw = o ne s witching c ycle) 0 0 32 t sw (total transition time = 32 32 t sw = 1024 t sw ) 0 1 8 t sw (total transition time = 8 32 t sw = 256 t sw ) 1 0 2 t sw (total transition time = 64 t sw ) 1 1 1 t sw (total transition time = 32 t sw ) table 115 . register 0x7b pgood1 flag masking bits bit name r/w description 7 soft start flag r/w if this bit is set to 1, th e sof t start flag is ignored by pgood1. this bit must be set to 0 to enable proper pgood1 debounce timing after the end of the soft start ramp. 6 cs1 fast ocp r/w if this bit is set to 1, the cs1 fast ocp flag is ignored by pgood1. 5 cs1 accurate ocp r/w if t his bit is set to 1, the cs1 accurate ocp flag is ignored by pgood1. 4 cs2 accurate ocp r/w if this bit is set to 1, the cs2 accurate ocp flag is ignored by pgood1. 3 uvp r/w if this bit is set to 1, the uvp flag is ignored by pgood1. 2 local ovp (fast and accurate) r/w if this bit is set to 1, the local ovp flag is ignored by pgood1. 1 load ovp r/w if this bit is set to 1, the load ovp flag is ignored by pgood1. 0 orfet r/w if this bit is set to 1, the orfet flag is ignored by pgood1. table 116 . register 0x7c pgood2 flag masking bits bit name r/w description 7 soft start flag r/w if this bit is set to 1, the soft start flag is ignored by pgood2. this bit must be set to 0 to enable proper pgood2 debounce timing after the end o f the soft start ramp. 6 cs1 fast ocp r/w if this bit is set to 1, the cs1 fast ocp flag is ignored by pgood2. 5 cs1 accurate ocp r/w if this bit is set to 1, the cs1 accurate ocp flag is ignored by pgood2. 4 cs2 accurate ocp r/w if this bit is set to 1 , the cs2 accurate ocp flag is ignored by pgood2. 3 uvp r/w if this bit is set to 1, the uvp flag is ignored by pgood2. 2 local ovp (fast and accurate) r/w if this bit is set to 1, the local ovp flag is ignored by pgood2. 1 load ovp r/w if this bit is s et to 1, the load ovp flag is ignored by pgood2. 0 orfet r/w if this bit is set to 1, the orfet flag is ignored by pgood2. adp1046a data sheet rev. 0 | page 78 of 88 table 117 . register 0x7d light load mode threshold settings bits bit name r/w description [7:6] reser ved r/w reserved. [5:4] debounce r/w after the sr outputs are turned on or off, any further transition of the thresholds is ignored for the amount of time programmed in th ese bits . this debounce is provided to avoid false transitions and improve noise imm unity. the debounce time is calculated as a number of pwm switching cycles ( t sw ). f or example, at 100 khz, t sw = 10 s, 64 t sw = 640 s . bit 5 bit 4 debounce time 0 0 0 t sw 0 1 64 t sw 1 0 128 t sw 1 1 256 t sw [3:2] light load mode ave raging speed r/w these bits set the averaging speed and resolution used for the light load mode threshold. faster speed corresponds to lower resolution and , therefore , to lower accuracy of the threshold. bit 3 bit 2 speed (resolution) 0 0 37.5 s ( 6 bits) 0 1 75 s (7 bits) 1 0 150 s (8 bits) 1 1 300 s (9 bits) [1:0] light load mode hysteresis r/w these bits set the amount of hysteresis applied to the light load mode threshold. the size of the lsb is affected by the speed and resoluti on selected in bits [3:2] . if the cs2 adc range of 120 mv is used with 8 - bit resolution, the lsb size is 120 mv/2 8 = 469 v. bit 1 bit 0 hysteresis (lsb) 0 0 3 0 1 8 1 0 12 1 1 16 table 118 . register 0x7f go byt e bits bit name r/w description [7:4] reserved r/w reserved. 3 filter go w this bit latches all the filter registers: register 0x 60 to register 0x67 and register 0x71 to register 0x75 . 2 frequency go w this bit latches register 0x3f and register 0x40 to prevent the switching frequency setting s from being temporarily incorrect. 1 pwm settings go w this bit latches register 0x41 to register 0x5c t o prevent the pwm setting s from being temporarily incorrect . note tha t register 0x5c[1] is not gated by this b it (register 0x7f[1] ) . a write to register 0x5c[1] immediately switch es the regulation point and frequency settings ; h owever, the correct modulation limit and filter setting s do not take effect until a subsequent f req uency go is executed using register 0x7 f[ 2 ] . for this reason , it is not recommended that the regulation point be changed on the fly using r egister 0x5c[1]. 0 voltage reference go w this bit latches register 0x31 to prevent the reference setting from being temporarily incorrect. data sheet adp1046a rev. 0 | page 79 of 88 eepro m registers refer to the i 2 c communication protocol specification for more information about how to write these commands to the adp1046a . table 119 . register 0x81 restore_default_all bit s bit name type description n/a restore_default_all s end byte download the f actory default s ettings from eeprom (page 0 of the main block ) into operating memory . t he password is also reset to the default value (0xff) . table 120 . register 0x82 store_user_all bits bit name type description n/a store_user_all s end byte copy the entire contents of operating memory ( registers ) in to eeprom ( page 1 of the main block). the eeprom must first be unlocked . table 121 . register 0x83 restore_user_all bits bit name type description n/a restore_user_all s end byte download the stored u ser s ettings from eeprom (page 1 of the main block ) into operating memory . the eeprom must first be unlocked . table 122 . register 0x84 eeprom_crc_chksum bits bit name type description [7:0] eeprom_crc_chksum r return the crc checksum value from the eeprom download operation . table 123 . register 0x85 eeprom_addr_offset bits bit name type de scription [15:0] eeprom_addr_offset r/w set the address offset of the current eeprom page . table 124 . register 0x86 eeprom_num_rd_bytes bits bit name type description [7:0] eeprom_num_rd_bytes r/w set the number of read bytes re turned when using the eeprom_data_xx command . table 125 . register 0x87 eeprom_page_erase bits bit name type description [7:4] reserved r reserved. [ 3 :0] eeprom_page_erase w perform a page erase on the selected eeprom page (page 4 to page 15). wait 35 ms after each page erase operation. the eeprom must first be unlocked. page 0 and page 1 are reserved for storing the default settings and user settings, respectively. the user cannot perform a page erase of page 0 or page 1. page 2 and page 3 are reserved for internal use ; do not erase the contents of page 2 or page 3 . table 126 . register 0x88 eeprom_password bits bit name type description [7:0] eeprom_password w write the password to this register two cons ecutive times to unlock the eeprom and/or to change the eeprom password . the factory default password is 0xff. to lock the eeprom, type any value other than the password to this register. table 127 . register 0x89 trim_password bit s bit name type description [7:0] trim_password r/w write the password to this register to unlock the trim registers for write access. write the trim password twice to unlock the register; write any other value to exit. the trim password is the same as th e eeprom password. adp1046a data sheet rev. 0 | page 80 of 88 table 128 . register 0x8a eeprom_info bits bit name type description variable eeprom_info block read block r ead from the eeprom info block. table 129 . register 0x8b eeprom_data_00 bits bit name type description variable eeprom_data_00 block read block r ead from the eeprom main block, page 0. the eeprom must first be unlocked. this page contains the factory default settings. table 130 . register 0x8c eeprom_data_ 01 bits bit name type description variable eeprom_data_01 block read block r ead from the eeprom main block, page 1 . the eeprom must first be unlocked. this page contains the user settings. table 131 . register 0x8d eeprom_data_02 bits bit name type description variable eeprom_data_02 block read block r ead from the eeprom main block, page 2 . this page contains internal settings and should not be written to or erased . table 1 32 . register 0x8e eeprom_data_03 bits bit name type description variable eeprom_data_03 block read block r ead from the eeprom main block, page 3 . this page contains internal settings and should not be written to or erased . table 133 . register 0x8f eeprom_data_0 4 bits bit name type description variable eeprom_data_04 block read/ write block read or write from the eeprom main block, page 4. to write to this page, the eeprom must first be unlocked. this page is available to the user for storing data. table 134 . register 0x90 eeprom_data_05 bits bit name type description variable eeprom_data_05 block read/ write block read or write from the eeprom main block, page 5 . to write to this page, the eeprom must first be unlocked. this page is av ailable to the user for storing data. table 135 . register 0x91 eeprom_data_06 bits bit name type description variable eeprom_data_06 block read/ write block read or write from the eeprom main block, page 6 . to write to this page, the eeprom must first be unlocked. this page is available to the user for storing data. table 136 . register 0x92 eeprom_data_07 bits bit name type description variable eeprom_data_07 block read/ write block read or write from th e eeprom main block, page 7 . to write to this page, the eeprom must first be unlocked. this page is available to the user for storing data. table 137 . register 0x93 eeprom_data_08 bits bit name type description variable eeprom_da ta_08 block read/ write block read or write from the eeprom main block, page 8 . to write to this page, the eeprom must first be unlocked. this page is available to the user for storing data. data sheet adp1046a rev. 0 | page 81 of 88 table 138 . register 0x94 eeprom_data_09 bits bit name type description variable eeprom_data_09 block read/ write block read or write from the eeprom main block, page 9 . to write to this page, the eeprom must first be unlocked. this page is available to the user for storing data. table 139 . register 0x95 eeprom_data_10 bits bit name type description variable eeprom_data_10 block read/ write block read or write from the eeprom main block, page 10 . to write to this page, the eeprom must first be unlocked. this page is av ailable to the user for storing data. table 140 . register 0x96 eeprom_data_11 bits bit name type description variable eeprom_data_11 block read/ write block read or write from the eeprom main block, page 11 . to write to this page , the eeprom must first be unlocked. this page is available to the user for storing data. table 141 . register 0x97 eeprom_data_12 bits bit name type description variable eeprom_data_12 block read/ write block read or write from t he eeprom main block, page 12 . to write to this page, the eeprom must first be unlocked. this page is available to the user for storing data. table 142 . register 0x98 eeprom_data_13 bits bit name type description variable eeprom_ data_13 block read/ write block read or write from the eeprom main block, page 13 . to write to this page, the eeprom must first be unlocked. this page is available to the user for storing data. table 143 . register 0x99 eeprom_data _14 bits bit name type description variable eeprom_data_14 block read/ write block read or write from the eeprom main block, page 14 . to write to this page, the eeprom must first be unlocked. this page is available to the user for storing data. table 144 . register 0x9a eeprom_data_15 bits bit name type description variable eeprom_data_15 block read/ write block read or write from the eeprom main block, page 15 . to write to this page, the eeprom must first be unlocked. this page i s available to the user for storing data. adp1046a data sheet rev. 0 | page 82 of 88 resonant mode operat ion the adp1046a supports control of a resonant converter. resonant converters are an alternative to traditional fixed frequency converters. they offer high switching frequency, small size, and high efficiency. figure 59 illustrates a widely used series resonant converter. q a q c q d q b c r l r i r i o sr2 sr1 c o r l 1 1012-037 figure 59 . series resonant converter resonant mode enable to enable the adp1046a to control a resonant switching con - verter, register 0x40 must be set to a value of 0x3f. in resonant mode, the pwm outputs have a fixed duty cycle with variable frequency. pwm timing in resonant mode with variable frequency control, outa and outb can only be high during the first half of the switching cycle (t a to t b ), whereas outc and outd can only be high during the second half of the switching cycle (t b to t c ), as shown in figure 60 . the frequency resolution of the control law is in steps of 10 ns. pwm1 (outa) pwm2 (outb) pwm3 (outc) pwm4 (outd) t a t b t c t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t period t period 1 1012-038 figure 60 . outa, outb, outc, and outd pwm timing diagram in resonant mode synchronous rectific ation in resonant mode c ontrol of the synchronous rectifiers in a resonant controller is a complicated issue. the adp1046a acsns comparator can be used to control the sr signals. in resonant mode operation, the sr1 output is driven by the rising edge of the acsns comparator, and the sr2 output is driven by the falling edge of the comparator, as shown in figure 61. v ds (sr2) acsns sync rect 1 (sr1) sync rect 2 (sr2) t d t e t f t 9 t 10 t 11 t 12 1 1012-040 figure 61 . sr1 and sr2 pwm timing diagram in resonant mode following is an example of how the adp1046a can be used in a series resonant topology and also achieve control of the synchro - nous rectifiers. the v ds voltage of sr2 ( see figure 61) can be used to control the sr signals. the acsns pin is connected to the divided - down sr2 v ds voltage. this provides the timing information for both synchronous rectifiers (see figure 62). c r l r i r i o sr2 sr1 c o r l r 1 r 2 acsns 1 1012-039 figu re 62 . resonant synchronous rectifier control circuit after the timing information is obtained, sr1 is driven by the rising edge of the acsns comparator, and sr2 is driven by the falling edge of the comparator, as shown in figure 61 . in this way, it is possible to achieve synchronous rectification. turn - on and turn - off delays can be programmed for the sr1 and sr2 signals individually. this example is not the only way to control the sr signal s. if the user has another method to control the sr signals, this method can be used to connect to the acsns input instead of the v ds voltage of sr2. when the adp1046a is used to control a resonant converter, i t is recommended that sr soft start be disabled during soft start of the device ( set register 0x0f[7] = 1). data sheet adp1046a rev. 0 | page 83 of 88 adjusting the timing of the pwm outputs to accurately adjust the timing of the pwm outputs, the follow ing registers can be used to set the dead tim e and delays of the pwm outputs: register 0x41, register 0x43, register 0x45 , register 0x47, register 0x49, register 0x4b, register 0x4d, register 0x4f, register 0x51, register 0x53, register 0x55, and register 0x57. the resolution for adjusting the dead t ime is 5 ns. see the resonant mode register descriptions section for more information . the software gui for the adp1046a can be used to set the frequency limit registers, as well as al l other settings related to the resonant mode of operation. frequency limit sett ing the minimum frequency is set by register 0x42 and the first four bits of register 0x44. for example, register 0x42 is set to 0xa0 (160 decimal) and bits[7:4] of register 0x 44 are set to 0xf (15 decimal). the maximum switching cycle is (160 16 + 15) 5 ns = 12.875 s the lowest switching frequency limit is 1/12.875 s = 77.7 khz the maximum frequency is set by register 0x46 and by bits[7:4] of register 0x48. for example, r egister 0x46 is set to 0x10 (16 decimal) and bits[7:4] of register 0x48 are set to 0x9 (9 decimal). the minimum switching cycle is (16 16 + 9) 5 ns = 1.325 s the highest switching frequency limit is 1/1.325 s = 755 khz feedback control in resonant mo de in contrast to a traditional fixed frequency pwm converter, the output voltage of a resonant converter is regulated by changing the switching frequency. when the adp1046a is operated in resonant mode, the sw itching frequency decreases when the sensed voltage is lower than the reference voltage. this makes the adp1046a capable of controlling a resonant converter in zero - voltage switching (zvs) mode. although the sw itching frequency is variable, the high frequency feedback voltage sampling frequency (vs3 pin s) is fixed at 400 khz. the parameters of the feedback filter are based on this frequency. the method for calculating the filter parameters (gains, zeros, and p oles) is the same as that for the fixed frequency pwm mode (see the digital filter section). soft start in resona nt mode during soft start, the reference voltage of the adp1046a ramps up. with the feedback loop closed, the switching frequency is reduced from the highest limit to a regulation value. the soft start timing settings and the filter settings are the same as those for the fixed frequency pwm mode (see the soft start section). light load operation (burst mode) to control the converter at very light load, the adp1046a can operate in burst mode. burst mode can be enabled or disabled using bits [7:6] of register 0x4a. when the desired switching frequency is higher than the burst mode threshold, the part enters burst mode. the threshold is determined by the maxi - mum frequency and the burst mode offset setting. the threshold value used to enter bur st mode is determined as follows: threshold value for burst mode = (( register 0x46 16) + register 0x48[7:4] ) + ( register 0x4a[5:0] 2) the threshold value used to exit burst mode is determined by the entrance value plus 0x10. for example, register 0x4 6 is set to 0x10 (16 decimal), bits[7:4] of register 0x48 are set to 0, and bits[5:0] of register 0x4a are set to 0x8 (8 decimal). the minimum switching cycle is (16 16 + 0) 5 ns = 1.28 s the highest switching frequency limit is 1/1.28 s = 781 khz th e threshold to enter burst mode is [(16 16 + 0) + (8 2)] 5 ns = 1.36 s when the desired switching frequency is higher than 1/1.36 s = 735 khz, the pwm outputs are shut down and the part enters burst mode. the threshold to exit burst mode is [(16 16 + 0) + (8 2) + 16] 5 ns = 1.44 s therefore, when the desired switching frequency becomes lower than 1/1.44 s = 694 khz, the pwm signals are reenabled, and the part exits burst mode. outaux pin in resonant mode in resonant mode, the outaux pin ca nnot be used as a control signal. however, outaux can be used as a fixed frequency pwm signal with a fixed duty cycle. protections in reson ant mode all of the flags and protections that are available in resonant mode behave in the same manner as in fixed f requency pwm mode. adp1046a da ta sheet rev. 0 | page 84 of 88 resonant mode regist er descriptions table 145 . register 0x40 pwm switching frequency setting in resonant mode bits bit name r/w description [7:6] reserved r/w reserved. [5:0] switching frequency r/w this regis ter sets the switching frequency of the pwm pins and enables resonant mode. to enable resonant mode, set these bits to 0x3f (111111). table 146 . register 0x41 outa rising edge dead time in resonant mode bits bit name r/w descripti on [7:0] t 1 (rising edge dead time of outa) r/w this register sets t 1 , which is the delay of the rising edge of outa from the start of the switching cycle, t a . each lsb corresponds to 5 ns of resolution. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t 1 (ns ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 1 1 1 1 1 1 1 1 1275 table 147 . register 0x42 lowest switching frequency limit setting (maximum switching cycle in resonant mode) bits bit name r/w descriptio n [7:0] lowest frequency r/w this register contains the eight msbs of the 12 - bit value of the lowest switching frequency (maxi - mum switching cycle) limit. this value is always used with the top four bits of register 0x44, which contain the four lsbs of th e lowest switching frequency limit. each lsb of the 12 - bit value corresponds to 5 ns of resolution for the switching cycle. for example, if register 0x42 is set to 0xa0 (160 decimal) and bits[7:4] of register 0x44 are set to 0xf (15 decimal), the maximum switching cycle is (160 16 + 15) 5 ns = 12.875 s, and the lowest switching frequency limit is 1/12.875 s = 77.7 khz. table 148 . register 0x43 outa falling edge dead time in resonant mode bits bit name r/w description [7:0] t 2 (falling edge dead time of outa) r/w thi s register sets t 2 , which is the difference between the falling edge of outa and the mid - point of the switching cycle, t b . each lsb corresponds to 5 ns of resolution. when the register value is from 0x00 to 0x7f, the falling edge of outa is trailing t b . w hen the value is from 0x80 to 0xff, the falling edge of outa is leading t b . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t 2 0 0 0 0 0 0 0 0 0 ns 0 0 0 0 0 0 0 1 5 ns trailing 0 1 1 1 1 1 1 1 635 ns trailing 1 0 0 0 0 0 0 0 640 ns leading 1 1 1 1 1 1 1 1 5 ns leading table 149 . register 0x44 lowest switching frequency limit setting (maximum switching cycle in resonant mode) bits bit name r/w description [7:4] lowest frequency r/w this register contains the four lsbs of the 12 - bit value of the lowest switching frequency (maxi- mum switching cycle) limit. this value is always used with the eight bits of register 0x42, which contain the eight msbs of the lowest swi tching frequency limit. each lsb of the 12 - bit value corresponds to 5 ns of resolution for the switching cycle. for example, if register 0x42 is set to 0xa0 (160 decimal) and bits[7:4] of register 0x44 are set to 0xf (15 decimal), the maximum switching cy cle is (160 16 + 15) 5 ns = 12.875 s, and the lowest switching frequency limit is 1/12.875 s = 77.7 khz. [3:0] reserved r/w reserved. data sheet adp1046a rev. 0 | page 85 of 88 table 150 . register 0x45 outb rising edge dead time in resonant mode bits bit name r/w description [7:0] t 3 (rising ed ge dead time of outb) r/w this register sets t 3 , which is the delay time of the rising edge of outb from the start of the switching cycle, t a . each lsb corresponds to 5 ns of resolution. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t 3 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 1 1 1 1 1 1 1 1 1275 table 151 . register 0x46 highest switching frequency limit setting (minimum switching cycle in resonant mode) bits bit name r/w description [7:0] highest frequency r/w this register contains the eight msbs of the 12 - bit value of the highest switching frequency (mini - mum switching cycle) limit. this value is always used with the top four bits of register 0x48, which contain the four lsbs of the high est switching frequency limit. each lsb of the 12 - bit value corresponds to 5 ns of resolution for the switching cycle. for example, if register 0x46 is set to 0x10 (16 decimal) and bits[7:4] of register 0x48 are set to 0x9 (9 decimal), the minimum switchi ng cycle is (16 16 + 9) 5 ns = 1.325 s, and the highest switching frequency limit is 1/1.325 s = 755 khz. it is recommended that the maximum frequency be limited to 1 mhz. table 152 . register 0x47 outb falling edge dead time in resonant mode bits bit name r/w description [7:0] t 4 (falling edge dead time of outb) r/w this register sets t 4 , which is the difference between the falling edge of outb and the mid - point of the switching cycle, t b . each lsb corresponds to 5 ns of resolution. when the register value is from 0x00 to 0x7f, the falling edge of outb is trailing t b . when the value is from 0x80 to 0xff, the falling edge of outb is leading t b . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t 4 0 0 0 0 0 0 0 0 0 ns 0 0 0 0 0 0 0 1 5 ns trailing 0 1 1 1 1 1 1 1 635 ns trailing 1 0 0 0 0 0 0 0 640 ns leading 1 1 1 1 1 1 1 1 5 ns leading table 153 . register 0x48 highest switching frequency limit setting (minimum switch ing cycle in resonant mode) bits bit name r/w description [7:4] highest frequency r/w this register contains the four lsbs of the 12 - bit value of the highest switching frequency (mini- mum switching cycle) limit. this value is always used with the eight bi ts of register 0x46, which contain the eight msbs of the highest switching frequency limit. each lsb of the 12 - bit value corresponds to 5 ns of resolution for the switching cycle. for example, if register 0x46 is set to 0x10 (16 decimal) and bits[7:4] of r egister 0x48 are set to 0x9 (9 decimal), the minimum switching cycle is (16 16 + 9) 5 ns = 1.325 s, and the highest switching frequency limit is 1/1.325 s = 755 khz. [3:0] reserved r/w reserved. adp1046a da ta sheet rev. 0 | page 86 of 88 table 154 . register 0x49 outc rising edge dead time in resonant mode bits bit name r/w description [7:0] t 5 (rising edge dead time of outc) r/w this register sets t 5 , which is the difference between the rising edge of outc and the mid - point of the switching cycle, t b . each lsb corresponds to 5 ns of resolution. when the register value is from 0x00 to 0x7f, the rising e dge of outc is trailing t b . when the value is from 0x80 to 0xff, the rising edge of outc is leading t b . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t 5 0 0 0 0 0 0 0 0 0 ns 0 0 0 0 0 0 0 1 5 ns trailing 0 1 1 1 1 1 1 1 635 ns trailing 1 0 0 0 0 0 0 0 640 ns leading 1 1 1 1 1 1 1 1 5 ns leading table 155 . register 0x4a burst mode operation in resonant mode bits bit name r/w description [7:6] burst mode enable r/w these bits are used to enable or disable burst mode operation. bit 7 bit 6 burst mode 0 0 disabled 0 1 enabled for normal operation, but disabled during soft start 1 0 disabled 1 1 enabled for normal operation and during soft start [5:0] burst mode offset r/w these bits, along with the highest switching frequency limit, determine the threshold value for enabling burst mode operation. for information about how to set this value, see the light load operation (burst mode) section. during burst mode, the pwm frequency is the maximum frequency limit set in register 0x46. table 156 . register 0x4b outc falling edge dead time in resonant mode bits bit name r/w description [ 7:0] t 6 (falling edge dead time of outc) r/w this register sets t 6 , which is the leading time of the falling edge of outc from the end of the switching cycle, t c . each lsb corresponds to 5 ns of resolution. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 t 6 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 1 1 1 1 1 1 1 1 1275 table 157 . register 0x4d outd rising edge dead time in resonant mode bits bit name r/w description [7:0] t 7 (rising edge de ad time of outd) r/w this register sets t 7 , which is the difference between the rising edge of outd and the mid - point of the switching cycle, t b . each lsb corresponds to 5 ns of resolution. when the register value is from 0x00 to 0x7f, the rising edge of outd is trailing t b . when the value is from 0x80 to 0xff, the rising edge of outd is leading t b . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t 7 0 0 0 0 0 0 0 0 0 ns 0 0 0 0 0 0 0 1 5 ns trailing 0 1 1 1 1 1 1 1 6 35 ns trailing 1 0 0 0 0 0 0 0 640 ns leading 1 1 1 1 1 1 1 1 5 ns leading data sheet adp1046a rev. 0 | page 87 of 88 table 158 . register 0x4f outd falling edge dead time in resonant mode bits bit name r/w description [7:0] t 8 (falling edge dead time of outd) r/w this register sets t 8 , which is the leading time of the falling edge of outd from the end of the switching cycle, t c . each lsb corresponds to 5 ns of resolution. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t 8 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 1 1 1 1 1 1 1 1 1275 table 159 . register 0x51 sr1 rising edge dead time in resonant mode bits bit name r/w description [7:0] t 9 (rising edge dead time of sr1) r/w this register sets t 9 , which is the delay time of the rising edge of sr1 from the acsns rising edge, t d . each lsb corresponds to 5 ns of resolution. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t 9 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 1 1 1 1 1 1 1 1 1275 table 160 . register 0x53 sr1 falling edge dead time in resonant mode bits bit name r/w description [7:0] t 10 (falling edge dead time of sr1) r/w this register sets t 10 , which is the lea ding time of the falling edge of sr1 from the acsns falling edge, t e . each lsb corresponds to 5 ns of resolution. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t 10 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 1 1 1 1 1 1 1 1 1275 table 161 . register 0x55 sr2 rising edge dead time in resonant mode bits bit name r/w description [7:0] t 11 (rising edge dead time of sr2) r/w this register sets t 11 , which is the delay time of the rising edge of sr2 from the acsns falling edge, t e . each lsb corresponds to 5 ns of resolution. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t 11 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 1 1 1 1 1 1 1 1 1275 table 162 . register 0x57 sr2 falling edge dead time in resonant mode bits bit name r/w description [7:0] t 12 (falling edge dead time of sr2) r/w this register sets t 12 , which is the leading time of the falling edge of sr2 from the acsns rising edge, t f . each lsb corresponds to 5 ns of resolution. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t 12 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 1 1 1 1 1 1 1 1 1275 adp1046a data sheet rev. 0 | page 88 of 88 outline dimensions compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bottom view top view pin 1 indi c ator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.25 3.10 sq 2.95 s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 63. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp-32-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adp1046aacpz-rl ?40c to +125c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-7 adp1046aacpz-r7 ?40c to +125c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-7 adp1046a-100-evalz adp1046a 100 w evaluation board adp1046adc1-evalz adp1046a daughter card ADP-I2C-USB-Z usb to i 2 c adapter 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d11012-0-2/13(0) |
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